#Map Resource Utilization Report file generated by Lattice Radiant Software (64-bit) 2024.1.1.259.1
#Generated on 10/21/24 01:06:12
#DESIGN = cpnx_riscv_rx_rd
#DEVICE = LFCPNX-100
#PACKAGE = BBG484
#OPERATING = Commercial
#PERFORMANCEGRADE = 8_High-Performance_1.0V
LUT4
Logic
LUT4
Distributed RAM
LUT4
Ripple Logic
PFU Registers IO Registers IO Buffers DSP MULT EBR Large RAM
cpnx_riscv_rx_rd26814(2)6714(0)3956(0)19986(0)9(0)67(10)6(0)52(0)2(0)
apb_interconnect0_inst65(0)0(0)0(0)4(0)0(0)0(0)0(0)0(0)0(0)
lscc_apb_interconnect_inst65(0)0(0)0(0)4(0)0(0)0(0)0(0)0(0)0(0)
apb_bus.u_lscc_apb_bus65(0)0(0)0(0)4(0)0(0)0(0)0(0)0(0)0(0)
u_lscc_apb_decoder12(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
genblk1[0].u_lscc_apb_decoder_sel4(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
genblk1[0].u_lscc_apb_decoder_comp4(4)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
genblk1[1].u_lscc_apb_decoder_sel3(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
genblk1[0].u_lscc_apb_decoder_comp3(3)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
genblk1[2].u_lscc_apb_decoder_sel5(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
genblk1[0].u_lscc_apb_decoder_comp5(5)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
u_lscc_apb_multiplexor53(53)0(0)0(0)4(4)0(0)0(0)0(0)0(0)0(0)
axi2ahbl_spi_flash_inst477(0)0(0)44(0)201(0)0(0)0(0)0(0)0(0)0(0)
lscc_axi2ahb_lite_inst477(477)0(0)44(44)201(201)0(0)0(0)0(0)0(0)0(0)
axi2apb0_inst229(0)0(0)42(0)190(0)0(0)0(0)0(0)0(0)0(0)
lscc_axi2apb_inst229(229)0(0)42(42)190(190)0(0)0(0)0(0)0(0)0(0)
axi_interconnect_0_inst7705(2)5592(0)900(0)5624(0)0(0)0(0)0(0)0(0)0(0)
lscc_axi_interconnect_inst7703(7703)5592(5592)900(900)5624(5624)0(0)0(0)0(0)0(0)0(0)
cpu_inst5172(1)72(0)1350(0)3550(0)0(0)0(0)6(0)18(0)0(0)
riscvrtos_inst5171(5171)72(72)1350(1350)3550(3550)0(0)0(0)6(6)18(18)0(0)
gpio0_inst114(0)0(0)0(0)89(0)8(0)8(0)0(0)0(0)0(0)
lscc_gpio_inst114(0)0(0)0(0)89(0)8(0)8(0)0(0)0(0)0(0)
genblk1.lscc_gpio_lmmi_0103(103)0(0)0(0)64(64)8(8)8(8)0(0)0(0)0(0)
genblk2.lscc_apb2lmmi_011(11)0(0)0(0)25(25)0(0)0(0)0(0)0(0)0(0)
lpddr4_inst10812(0)1050(0)1478(0)8940(0)1(0)49(0)0(0)33(0)0(0)
lscc_lpddr4_mc_inst10812(0)1050(0)1478(0)8940(99)1(0)49(0)0(0)33(0)0(0)
AXI_BI.u_axi_if980(0)618(0)330(0)2146(0)0(0)0(0)0(0)8(0)0(0)
u_rd370(59)102(0)306(0)1030(93)0(0)0(0)0(0)8(0)0(0)
ASYNC.u_ctrl_fifo25(0)66(0)0(0)67(0)0(0)0(0)0(0)0(0)0(0)
u_fifo_dc25(25)66(66)0(0)67(67)0(0)0(0)0(0)0(0)0(0)
u_reorder_buff286(278)36(0)306(306)870(814)0(0)0(0)0(0)8(0)0(0)
EBR_CTRL[0].ASYNC.u_enable_bus_sync1(1)0(0)0(0)5(5)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[0].ASYNC.u_not_empty_sync0(0)0(0)0(0)2(2)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[1].ASYNC.u_enable_bus_sync1(1)0(0)0(0)5(5)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[1].ASYNC.u_not_empty_sync0(0)0(0)0(0)2(2)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[2].ASYNC.u_enable_bus_sync1(1)0(0)0(0)5(5)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[2].ASYNC.u_not_empty_sync0(0)0(0)0(0)2(2)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[3].ASYNC.u_enable_bus_sync1(1)0(0)0(0)5(5)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[3].ASYNC.u_not_empty_sync0(0)0(0)0(0)2(2)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[4].ASYNC.u_enable_bus_sync1(1)0(0)0(0)5(5)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[4].ASYNC.u_not_empty_sync0(0)0(0)0(0)2(2)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[5].ASYNC.u_enable_bus_sync1(1)0(0)0(0)5(5)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[5].ASYNC.u_not_empty_sync0(0)0(0)0(0)2(2)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[6].ASYNC.u_enable_bus_sync1(1)0(0)0(0)5(5)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[6].ASYNC.u_not_empty_sync0(0)0(0)0(0)2(2)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[7].ASYNC.u_enable_bus_sync1(1)0(0)0(0)5(5)0(0)0(0)0(0)0(0)0(0)
EBR_CTRL[7].ASYNC.u_not_empty_sync0(0)0(0)0(0)2(2)0(0)0(0)0(0)0(0)0(0)
u_ctrl_dpram0(0)36(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
lscc_distributed_dpram_inst0(0)36(36)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
u_lpddr4_mc_rd_rtrn_ebr_inst0(0)0(0)0(0)0(0)0(0)0(0)0(0)8(0)0(0)
lscc_ram_dp_inst0(0)0(0)0(0)0(0)0(0)0(0)0(0)8(0)0(0)
mem_main0(0)0(0)0(0)0(0)0(0)0(0)0(0)8(0)0(0)
NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[0].no_init.u_mem00(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)0(0)
NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[1].no_init.u_mem00(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)0(0)
NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[2].no_init.u_mem00(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)0(0)
NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[3].no_init.u_mem00(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)0(0)
NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[4].no_init.u_mem00(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)0(0)
NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[5].no_init.u_mem00(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)0(0)
NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[6].no_init.u_mem00(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)0(0)
NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[7].no_init.u_mem00(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)0(0)
u_wr610(411)516(0)24(10)1116(633)0(0)0(0)0(0)0(0)0(0)
ASYNC.u_ctrl_fifo31(0)60(0)0(0)63(0)0(0)0(0)0(0)0(0)0(0)
u_fifo_dc31(31)60(60)0(0)63(63)0(0)0(0)0(0)0(0)0(0)
ASYNC.u_data_fifo45(0)438(0)14(0)330(0)0(0)0(0)0(0)0(0)0(0)
u_fifo_dc45(45)438(438)14(14)330(330)0(0)0(0)0(0)0(0)0(0)
u_int_fifo22(0)12(0)0(0)48(0)0(0)0(0)0(0)0(0)0(0)
u_fifo22(22)12(12)0(0)48(48)0(0)0(0)0(0)0(0)0(0)
u_rsp_fifo101(0)6(0)0(0)42(0)0(0)0(0)0(0)0(0)0(0)
u_fifo101(101)6(6)0(0)42(42)0(0)0(0)0(0)0(0)0(0)
i_apb_cdc72(72)0(0)0(0)232(232)0(0)0(0)0(0)0(0)0(0)
u_ctrl_wrap9628(0)432(0)1130(0)6390(0)0(0)0(0)0(0)25(0)0(0)
u_controller9628(9628)432(432)1130(1130)6390(6390)0(0)0(0)0(0)25(25)0(0)
u_lp4mem132(48)0(0)18(8)73(9)1(0)49(0)0(0)0(0)0(0)
CA_GRP_ENA.u_ca_grp17(17)0(0)10(10)23(23)1(1)9(9)0(0)0(0)0(0)
u1_clock_sync63(0)0(0)0(0)41(0)0(0)0(0)0(0)0(0)0(0)
u1_mem_sync63(63)0(0)0(0)41(41)0(0)0(0)0(0)0(0)0(0)
u_dq_dqs_dm0(0)0(0)0(0)0(0)0(0)40(40)0(0)0(0)0(0)
u_pll4(4)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
osc0_inst0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
lscc_osc_inst0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
pll0_inst1(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
lscc_pll_inst1(1)0(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)
spi_flash1_inst1698(0)0(0)52(0)1041(0)0(0)0(0)0(0)1(0)0(0)
lscc_spi_flash_inst1698(1698)0(0)52(52)1041(1041)0(0)0(0)0(0)1(1)0(0)
system0_inst539(0)0(0)90(0)347(0)0(0)0(0)0(0)0(0)2(0)
lscc_sys_mem_inst539(0)0(0)90(0)347(0)0(0)0(0)0(0)0(0)2(0)
AXI4_ARB.u_arbiter0(0)0(0)0(0)1(1)0(0)0(0)0(0)0(0)0(0)
CORE_MEMORY.genblk1.u_lscc_mem02(0)0(0)0(0)2(0)0(0)0(0)0(0)0(0)2(0)
intf_AXI4.lram.ulram_02(2)0(0)0(0)2(2)0(0)0(0)0(0)0(0)2(0)
genblk2[0].genblk3.ulram_core00(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)
genblk2[1].genblk3.ulram_core00(0)0(0)0(0)0(0)0(0)0(0)0(0)0(0)1(1)
bridge_s0.genblk1.bridge_s0537(537)0(0)90(90)344(344)0(0)0(0)0(0)0(0)0(0)