Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved. Fri Oct 18 10:50:40 2024 Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -stopzero -hsp m -exp \ nbrForceHoldTimeCorrection=1:parPathBased=ON cpnx_riscv_rx_rd_impl_1_map.udb \ cpnx_riscv_rx_rd_impl_1.udb Cost Table Summary Level/ Number Estimated Timing Estimated Worst Timing Run Run Cost [udb] Unrouted Worst Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----------- ------ --------------- ----------- ---- ------ 5_1 * 0 -1.672 2528 0.064 0 58:06 Completed * : Design saved. Total (real) run time for 1-seed: 58 mins 16 secs par done! Lattice Place and Route Report for Design "cpnx_riscv_rx_rd_impl_1_map.udb" Fri Oct 18 10:50:40 2024 Best Par Run PAR: Place And Route Radiant Software (64-bit) 2024.1.1.259.1. Command Line: par -w -t 1 -cores 1 -stopzero -hsp m -exp \ nbrForceHoldTimeCorrection=1:parPathBased=ON cpnx_riscv_rx_rd_impl_1_map.udb \ cpnx_riscv_rx_rd_impl_1_par.dir/5_1.udb Loading cpnx_riscv_rx_rd_impl_1_map.udb ... Loading device for application GENERIC from file 'jd5d80.nph' in environment: C:/lscc/radiant/2024.1/ispfpga. Package Status: Final Version 16. Performance Hardware Data Status: Final Version 3.9. Design: cpnx_riscv_rx_rd Family: LFCPNX Device: LFCPNX-100 Package: BBG484 Performance Grade: 8_High-Performance_1.0V Constraint Summary Total number of constraints: 210 Total number of constraints dropped: 0 WARNING <71003020> - par: Top module port 'TCK' does not connect to anything. WARNING <71003020> - par: Top module port 'TMS' does not connect to anything. WARNING <71003020> - par: Top module port 'TDI' does not connect to anything. WARNING <71003020> - par: Top module port 'TDO' does not connect to anything. WARNING <71003020> - par: Top module port 'TCK' does not connect to anything. WARNING <71003020> - par: Top module port 'TMS' does not connect to anything. WARNING <71003020> - par: Top module port 'TDI' does not connect to anything. WARNING <71003020> - par: Top module port 'TDO' does not connect to anything. WARNING <71241014> - par: The PLL clock port [ddr_pll_refclk_i] is assigned to a non-PLL clock dedicated pin [U3], which might affect the clock performance. Use dedicated PLL clock resources for the port. Device SLICE utilization summary after final SLICE packing: SLICE 35941/39936 89% used Number of Signals: 67936 Number of Connections: 216507 Device utilization summary: VHI 1/1 100% used SIOLOGIC 8/300 3% used DCC 1/62 2% used EBR 52/208 25% used MULT9 12/312 4% used MULT18 6/156 4% used MULT18X36 2/78 3% used REG18 10/312 3% used PREADD9 12/312 4% used LRAM 2/7 29% used DIFFIO18A 6/66 9% used 6/66 9% bonded DDRDLL 1/2 50% used DQSBUFA 4/11 36% used IOLOGIC 50/132 38% used SEIO18A 57/132 43% used 57/132 43% bonded SEIO33 16/299 5% used 16/167 9% bonded ECLKDIV 1/12 8% used ECLKSYNC 1/12 8% used OSC 1/1 100% used PLL 2/4 50% used CONFIG_JTAG 1/1 100% used IVREF 4/11 36% used SLICE 35941/39936 90% used LUT 37484/79872 47% used REG 19986/79872 25% used Pin Constraint Summary: 66 out of 67 pins locked (98% locked). INFO: signal 'cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.IbCuo3aEvk5cF25j4DHzkJGG2F.NbqAaKcoy7LeAHb1' driving mixed DCC load types requires multi-feedlines. . . INFO: signal 'cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.IbCuo3aEvk5cF25j4DHzkJGG2F.NbqAaKcoy7LeAHb1' driving mixed DCC load types requires multi-feedlines. . Starting Placer Phase 0 (HIER). CPU time: 1 mins 16 secs , REAL time: 1 mins 18 secs ........... Finished Placer Phase 0 (HIER). CPU time: 2 mins 12 secs , REAL time: 2 mins 13 secs . Starting Placer Phase 1. CPU time: 2 mins 14 secs , REAL time: 2 mins 16 secs .. .. ................... Placer score = 18201587. Finished Placer Phase 1. CPU time: 23 mins 52 secs , REAL time: 24 mins 41 secs Starting Placer Phase 2. . Placer score = 17951328 Finished Placer Phase 2. CPU time: 25 mins 5 secs , REAL time: 25 mins 56 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 26 (0%) PLL : 2 out of 4 (50%) PCS : 0 out of 2 (0%) DCS : 0 out of 2 (0%) DCC : 1 out of 62 (1%) ECLKDIV : 1 out of 12 (8%) PCLKDIV : 0 out of 2 (0%) OSC : 1 out of 1 (100%) Global Clocks: PRIMARY "osc0_inst_lf_clk_out_o_net" from LFCLKOUT on comp "osc0_inst.lscc_osc_inst.gen_osca.u_OSC_A.OSCA_inst" on site "OSC_CORE_R1C137", clk load = 0, ce load = 0, sr load = 0 PRIMARY "lpddr4_inst.lscc_lpddr4_mc_inst.sclk_o" from comp "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst" on ECLKDIV_CORE site "ECLKDIV_CORE_R73C74B", clk load = 6097, ce load = 0, sr load = 0 PRIMARY "osc0_inst_hf_clk_out_o_net" from HFCLKOUT on comp "osc0_inst.lscc_osc_inst.gen_osca.u_OSC_A.OSCA_inst" on site "OSC_CORE_R1C137", clk load = 1, ce load = 0, sr load = 0 PRIMARY "pll0_inst_clkop_o_net" from CLKOP on comp "pll0_inst.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_ULC", clk load = 12035, ce load = 0, sr load = 0 PRIMARY "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.clkop_o" from CLKOP on comp "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_LLC", clk load = 1, ce load = 0, sr load = 0 PRIMARY "spi_flash1_inst.lscc_spi_flash_inst.spi_clk" from F0 on comp "spi_flash1_inst.lscc_spi_flash_inst.un5_spi_clk_cZ" on site "R38C74A", clk load = 344, ce load = 0, sr load = 0 PRIMARY "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.IbCuo3aEvk5cF25j4DHzkJGG2F.NbqAaKcoy7LeAHb1" from JTCK on comp "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.IbCuo3aEvk5cF25j4DHzkJGG2F.genblk2.jtag.jtagg_u" on site "TCONFIG_JTAG_CORE145", clk load = 58, ce load = 0, sr load = 0 PRIMARY "cpu_inst_system_resetn_o_net" from F0 on comp "cpu_inst.riscvrtos_inst.IeF7agekvg8g049yF9Je.IfLEI7caHLxlLxjaqh21be38kfLLkKvwGp48hshA.In3l2KesC0qKprI2Gjo4kG1D" on site "R38C74C", clk load = 0, ce load = 0, sr load = 6493 PRIMARY "lpddr4_inst.lscc_lpddr4_mc_inst.srst_n" from Q0 on comp "lpddr4_inst.lscc_lpddr4_mc_inst.srst_n_reg.ff_inst" on site "R38C73A", clk load = 0, ce load = 1, sr load = 4188 PRIMARY "lpddr4_inst.lscc_lpddr4_mc_inst.phy_srst_n" from Q0 on comp "lpddr4_inst.lscc_lpddr4_mc_inst.phy_srst_n_reg.ff_inst" on site "R38C73C", clk load = 0, ce load = 1, sr load = 925 PRIMARY "lpddr4_inst.lscc_lpddr4_mc_inst.arst_n" from Q0 on comp "lpddr4_inst.lscc_lpddr4_mc_inst.arst_n_reg.ff_inst" on site "R72C71A", clk load = 0, ce load = 0, sr load = 781 PRIMARY "cpu_inst.riscvrtos_inst.NhzIwgk9ntaBs9hu6Iowge96EHqAigmbsfJd3j48qs0oovq3w3vw7aEmpt7nFlqp2quKDA" from Q0 on comp "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.I3pznmxwAhGbm8oB9j1odf1HDKBsa3e.ff_inst" on site "R72C72A", clk load = 0, ce load = 0, sr load = 393 PRIMARY "cpu_inst.riscvrtos_inst.NbAnIwL3pee6EwvsD1j3HGm5IF" from F0 on comp "cpu_inst.riscvrtos_inst.IeF7agekvg8g049yF9Je.IfLEI7caHLxlLxjaqh21be38kfLLkKvwGp48hshA.IbAnIwL3pee6EwvsD1j3HGm5IF" on site "R72C73A", clk load = 0, ce load = 0, sr load = 372 PRIMARY "cpu_inst.riscvrtos_inst.IbIKu9Euqshrx92EKce1vmk7bJ8Dhit4eusig379a056mB.NccrsssLqvEkkx2EfsGr0ng34v2812oAJH5Bwt25o8aDcj" from F0 on comp "cpu_inst.riscvrtos_inst.IbIKu9Euqshrx92EKce1vmk7bJ8Dhit4eusig379a056mB.IB787Gmod6tK62c1t4G4fK2Fb9D7mH4BE86tKsJ5s7JdsoKoq2f" on site "R72C74A", clk load = 0, ce load = 328, sr load = 1 PRIMARY DCC "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.NbbICH" from comp "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.IbCuo3aEvk5cF25j4DHzkJGG2F.Iohm428if6m0yb9tuqsdusxw" on DCC site "DCC_T0", total # of clk loads = 83 - DCC input "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.IbCuo3aEvk5cF25j4DHzkJGG2F.NbqAaKcoy7LeAHb1" from JTCK on comp "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.IbCuo3aEvk5cF25j4DHzkJGG2F.genblk2.jtag.jtagg_u" on site "TCONFIG_JTAG_CORE145" PRIMARY : 15 out of 16 (93%) Edge Clocks: ECLK "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w": BANK3_ECLK1 - From GPLL_CLKOS "PLL_LLC".CLKOS, driver "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst". ECLK "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w": BANK4_ECLK1 - From GPLL_CLKOS "PLL_LLC".CLKOS, driver "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst". I/O Usage Summary (final): 16 out of 299 (5.4%) SEIO33 sites used. 16 out of 167 (9.6%) bonded SEIO33 sites used. Number of SEIO33 components: 16; differential: 0 Number of Vref pins used: 0 51 out of 132 (38.6%) SEIO18 sites used. 51 out of 132 (38.6%) bonded SEIO18 sites used. Number of SEIO18 components: 51; differential: 6 6 out of 66 (9.1%) DIFFIO18 sites used. 6 out of 66 (9.1%) bonded DIFFIO18 sites used. Number of DIFFIO18 components: 6; differential: 6 I/O Bank Usage Summary: +----------+----------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+----------------+------------+------------+------------+ | 0 | 7 / 24 ( 29%) | 3.3V | - | - | | 1 | 9 / 39 ( 23%) | 3.3V | - | - | | 2 | 0 / 32 ( 0%) | - | - | - | | 3 | 22 / 48 ( 45%) | 1.1V | - | - | | 4 | 33 / 48 ( 68%) | 1.1V | - | - | | 5 | 2 / 36 ( 5%) | 1.8V | - | - | | 6 | 0 / 32 ( 0%) | - | - | - | | 7 | 0 / 40 ( 0%) | - | - | - | +----------+----------------+------------+------------+------------+ Total Placer CPU time: 25 mins 8 secs , REAL time: 25 mins 58 secs Checksum -- place: be1eaac1d05d414d51f54c9ae037092357920f Writing design to file cpnx_riscv_rx_rd_impl_1_par.dir/5_1.udb ... WARNING <71003020> - par: Top module port 'TCK' does not connect to anything. WARNING <71003020> - par: Top module port 'TMS' does not connect to anything. WARNING <71003020> - par: Top module port 'TDI' does not connect to anything. WARNING <71003020> - par: Top module port 'TDO' does not connect to anything. WARNING <71241014> - par: The PLL clock port [ddr_pll_refclk_i] is assigned to a non-PLL clock dedicated pin [U3], which might affect the clock performance. Use dedicated PLL clock resources for the port. Start NBR router at 11:17:07 10/18/24 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in timing report. You should always run the timing tool to verify your design. ***************************************************************** Starting routing resource preassignment WARNING <62243001> - par: The external feedback signal lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.clkop_o for PLL_CORE instance lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst drives neither primary nor edge clock loads. Please review this PLL feedback connection in your design. INFO <62244000> - par: The external feedback signal lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.clkop_o for PLL_CORE instance lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst will use the primary clock network. Preassignment Summary: -------------------------------------------------------------------------------- 10342 connections routed with dedicated routing resources 14 global clock signals routed 63889 connections routed (of 216507 total) (29.51%) --------------------------------------------------------- Clock routing summary: Primary clocks (60 used out of 64 available): Signal "pll0_inst_clkop_o_net" (7, 23, 39, 55) Clock loads: 12035 out of 12035 routed (100.00%) Data loads: 0 out of 1 routed ( 0.00%) Signal "cpu_inst_system_resetn_o_net" (10, 26, 42, 58) Control loads: 6493 out of 6493 routed (100.00%) Data loads: 0 out of 3 routed ( 0.00%) Signal "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.IbCuo3aEvk5cF25j4DHzkJGG2F.NbqAaKcoy7LeAHb1" (5, 21, 37, 53) Clock loads: 58 out of 58 routed (100.00%) Data loads: 1 out of 1 routed (100.00%) Signal "cpu_inst.riscvrtos_inst.Ibb45mqq1Dymg0ysCxp1KEgkwALCmfHgtc28aCq.NbbICH" (14, 30, 46, 62) Clock loads: 83 out of 83 routed (100.00%) Signal "cpu_inst.riscvrtos_inst.NhzIwgk9ntaBs9hu6Iowge96EHqAigmbsfJd3j48qs0oovq3w3vw7aEmpt7nFlqp2quKDA" (0, 16, 32, 48) Control loads: 393 out of 393 routed (100.00%) Data loads: 0 out of 34 routed ( 0.00%) Signal "cpu_inst.riscvrtos_inst.IbIKu9Euqshrx92EKce1vmk7bJ8Dhit4eusig379a056mB.NccrsssLqvEkkx2EfsGr0ng34v2812oAJH5Bwt25o8aDcj" (15, 31, 47, 63) Control loads: 329 out of 329 routed (100.00%) Data loads: 0 out of 95 routed ( 0.00%) Signal "cpu_inst.riscvrtos_inst.NbAnIwL3pee6EwvsD1j3HGm5IF" (9, 25, 41, 57) Control loads: 372 out of 372 routed (100.00%) Signal "osc0_inst_lf_clk_out_o_net" (11, 27, 43, 59) Data loads: 0 out of 1 routed ( 0.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.arst_n" (13, 29, 45, 61) Control loads: 781 out of 781 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.srst_n" (8, 24, 40, 56) Control loads: 4189 out of 4189 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.phy_srst_n" (12, 28, 44, 60) Control loads: 926 out of 926 routed (100.00%) Data loads: 0 out of 2 routed ( 0.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.sclk_o" (1, 17, 33, 49) Clock loads: 6097 out of 6097 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.clkop_o" (2, 18, 34, 50) Clock loads: 1 out of 1 routed (100.00%) Signal "osc0_inst_hf_clk_out_o_net" (3, 19, 35, 51) Clock loads: 1 out of 1 routed (100.00%) Signal "spi_flash1_inst.lscc_spi_flash_inst.spi_clk" (4, 20, 36, 52) Clock loads: 344 out of 344 routed (100.00%) Data loads: 0 out of 1 routed ( 0.00%) Other clocks: Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w" Clock loads: 55 out of 55 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[2]" Clock loads: 9 out of 9 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[3]" Clock loads: 9 out of 9 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[0]" Clock loads: 9 out of 9 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[1]" Clock loads: 9 out of 9 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[2]" Clock loads: 8 out of 8 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[3]" Clock loads: 8 out of 8 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[1]" Clock loads: 8 out of 8 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[0]" Clock loads: 8 out of 8 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[3]" Clock loads: 1 out of 1 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[2]" Clock loads: 1 out of 1 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[0]" Clock loads: 1 out of 1 routed (100.00%) Signal "lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[1]" Clock loads: 1 out of 1 routed (100.00%) Signal "ddr_pll_refclk_i_c" Clock loads: 1 out of 1 routed (100.00%) Signal "pll0_inst.lscc_pll_inst.intclkop_w" Clock loads: 1 out of 1 routed (100.00%) --------------------------------------------------------- -------------------------------------------------------------------------------- Completed routing resource preassignment +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Routing in Serial Mode ...... +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Start NBR section for initial routing at 11:18:32 10/18/24 Level 4, iteration 1 30009(0.70%) conflicts; 0(0.00%) untouched conn; 577775 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.442ns/-577.776ns; real time: 2 mins 46 secs Info: Initial congestion level at 75.00% usage is 0 Info: Initial congestion area at 75.00% usage is 24 (0.21%) Start NBR section for normal routing at 11:19:49 10/18/24 Level 4, iteration 1 23550(0.55%) conflicts; 0(0.00%) untouched conn; 639622 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.437ns/-639.623ns; real time: 3 mins 24 secs Level 4, iteration 2 8053(0.19%) conflicts; 0(0.00%) untouched conn; 665425 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.482ns/-665.426ns; real time: 3 mins 54 secs Level 4, iteration 3 3827(0.09%) conflicts; 0(0.00%) untouched conn; 731815 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.610ns/-731.816ns; real time: 4 mins 13 secs Level 4, iteration 4 2307(0.05%) conflicts; 0(0.00%) untouched conn; 767565 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.614ns/-767.566ns; real time: 4 mins 28 secs Level 4, iteration 5 1176(0.03%) conflicts; 0(0.00%) untouched conn; 767565 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.614ns/-767.566ns; real time: 4 mins 34 secs Level 4, iteration 6 569(0.01%) conflicts; 0(0.00%) untouched conn; 766034 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.687ns/-766.035ns; real time: 4 mins 47 secs Level 4, iteration 7 300(0.01%) conflicts; 0(0.00%) untouched conn; 766034 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.687ns/-766.035ns; real time: 4 mins 49 secs Level 4, iteration 8 208(0.00%) conflicts; 0(0.00%) untouched conn; 806097 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-806.098ns; real time: 4 mins 59 secs Level 4, iteration 9 86(0.00%) conflicts; 0(0.00%) untouched conn; 806097 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-806.098ns; real time: 5 mins 1 secs Level 4, iteration 10 62(0.00%) conflicts; 0(0.00%) untouched conn; 790664 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-790.665ns; real time: 5 mins 10 secs Level 4, iteration 11 20(0.00%) conflicts; 0(0.00%) untouched conn; 790664 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-790.665ns; real time: 5 mins 11 secs Level 4, iteration 12 11(0.00%) conflicts; 0(0.00%) untouched conn; 794313 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.314ns; real time: 5 mins 20 secs Level 4, iteration 13 6(0.00%) conflicts; 0(0.00%) untouched conn; 794313 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.314ns; real time: 5 mins 20 secs Level 4, iteration 14 4(0.00%) conflicts; 0(0.00%) untouched conn; 794511 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.512ns; real time: 5 mins 29 secs Level 4, iteration 15 2(0.00%) conflicts; 0(0.00%) untouched conn; 794511 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.512ns; real time: 5 mins 30 secs Level 4, iteration 16 1(0.00%) conflict; 0(0.00%) untouched conn; 794885 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.886ns; real time: 5 mins 38 secs Level 4, iteration 17 1(0.00%) conflict; 0(0.00%) untouched conn; 794885 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.886ns; real time: 5 mins 39 secs Level 4, iteration 18 1(0.00%) conflict; 0(0.00%) untouched conn; 794934 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.935ns; real time: 5 mins 48 secs Level 4, iteration 19 1(0.00%) conflict; 0(0.00%) untouched conn; 794934 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.935ns; real time: 5 mins 49 secs Level 4, iteration 20 1(0.00%) conflict; 0(0.00%) untouched conn; 794885 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.886ns; real time: 5 mins 58 secs Level 4, iteration 21 1(0.00%) conflict; 0(0.00%) untouched conn; 794885 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.886ns; real time: 5 mins 59 secs Level 4, iteration 22 1(0.00%) conflict; 0(0.00%) untouched conn; 794929 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.930ns; real time: 6 mins 9 secs Level 4, iteration 23 1(0.00%) conflict; 0(0.00%) untouched conn; 794929 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.930ns; real time: 6 mins 9 secs Level 4, iteration 24 0(0.00%) conflict; 0(0.00%) untouched conn; 794985 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.986ns; real time: 6 mins 18 secs Start NBR section for setup/hold timing optimization with effort level 3 at 11:23:20 10/18/24 Level 4, iteration 0 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<hold >: 0.064ns/0.000ns; real time: 27 mins 41 secs Level 4, iteration 0 0(0.00%) conflict; 0(0.00%) untouched conn; 815050 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-815.051ns; real time: 28 mins 32 secs Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 815050 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-815.051ns; real time: 28 mins 32 secs Start NBR section for post-routing at 11:46:24 10/18/24 0(0.00%) conflict; 0(0.00%) untouched conn; 794985 (nbr) score; Estimated worst slack/total negative slack<setup>: -1.672ns/-794.986ns; real time: 29 mins 29 secs End NBR router with 0 unrouted connection(s) Checksum -- route: f4028e53865ce75dcb272b3960f32d00958279bc Total CPU time 30 mins 46 secs Total REAL time: 31 mins 34 secs Completely routed. End of route. 216507 routed (100.00%); 0 unrouted. Writing design to file cpnx_riscv_rx_rd_impl_1_par.dir/5_1.udb ... All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Estimated worst slack<setup/<ns>> = -1.672 PAR_SUMMARY::Timing score<setup/<ns>> = 2.528 PAR_SUMMARY::Estimated worst slack<hold/<ns>> = 0.064 PAR_SUMMARY::Timing score<hold/<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Note: user must run 'timing' for timing closure signoff. Total CPU Time: 56 mins 36 secs Total REAL Time: 58 mins 16 secs Peak Memory Usage: 2606.57 MB par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2024 Lattice Semiconductor Corporation, All rights reserved.