proj_1 (impl_1)
Synthesis -
Compiler Report
Compiler Constraint Applicator
Pre-mapping Report
Clock Summary
Clock Conversion
Mapper Report
Timing Report
Performance Summary
Clock Relationships
Interface Information
Detailed Report for Clocks
Clock: cpu_ipgen_vex_jtag_bridge_LIFCL_14s_0s_0b1_0b0_0b0_0x04000|bbICH_inferred_clock
Starting Points with Worst Slack
Ending Points with Worst Slack
Worst Path Information
Clock: cpu_ipgen_vex_jtag_bridge_LIFCL_14s_0s_0b1_0b0_0b0_0x04000|bqAaKcoy7LeAHb1_inferred_clock
Clock: new_lpddr4_ipgen_clock_sync_1s_4s_0s_4|sclk_o_inferred_clock
Clock: pll0_ipgen_lscc_pll_Z137_layer0|clkop_o_inferred_clock
Clock: spi_flash1_inst_spi_clk
Clock: System
Resource Utilization
Constraint Checker Report (10:37 18-Oct)
Unconstrained Start/End Points
Inapplicable constraints
Applicable constraints with issues
Constraints with matching wildcard expressions
Library Report
Session Log (10:37 18-Oct)