Lattice Mapping Report File

Design:  cpnx_riscv_rx_rd
Family:  LFCPNX
Device:  LFCPNX-100
Package: BBG484
Performance Grade:  8_High-Performance_1.0V

Mapper:    version Radiant Software (64-bit) 2024.1.1.259.1
Mapped on: Fri Oct 18 10:49:41 2024

Design Information

Command line:   map -pdc C:/LAB3/SRC/LAB3_MAS_ARROW_pinout.pdc -i
     cpnx_riscv_rx_rd_impl_1_syn.udb -o cpnx_riscv_rx_rd_impl_1_map.udb -mp
     cpnx_riscv_rx_rd_impl_1.mrp -hierrpt -gui -msgset
     C:/LAB3/WS/cpnx_riscv_rx_rd/promote.xml

Design Summary

   Number of registers:        19995 out of 80769 (25%)
      Number of SLICE         registers: 19986 out of 79872 (25%)
      Number of PIO Input     registers:    8 out of   299 (3%)
      Number of PIO Output    registers:    1 out of   299 (<1%)
      Number of PIO Tri-State registers:    0 out of   299 (0%)
   Number of LUT4s:            37484 out of 79872 (47%)
      Number used as logic LUT4s:                       26814
      Number used as distributed RAM:                   6714 (6 per 16X4 RAM)
      Number used as ripple logic:                      3956 (2 per CCU2)
   Number of PIOs used/reserved:   80 out of   299 (27%)
      Number of PIOs reserved:      7 (per sysConfig and/or prohibit constraint)
      Number of PIOs used:         73
        Number of PIOs used for single ended IO:        61
        Number of PIO pairs used for differential IO:    6
        Number allocated to regular speed PIOs:    16 out of  167 (10%)
        Number allocated to high speed PIOs:       57 out of  132 (43%)
   Number of Dedicated IO used for ADC/PCS/PCIE:    0 out of   60 (0%)
   Number of IDDR/ODDR/TDDR functions used:    121 out of   730 (17%)
      Number of IDDR functions:               32
                IDDRX4:          32
      Number of ODDR functions:               49
                ODDRX4:          49
      Number of TDDR functions:               40
                TDDRX4:          40
   Number of IOs using at least one DDR function: 49 (5 differential)
      Number of IOs using IDDR only:           0 (0 differential)
      Number of IOs using ODDR only:           9 (1 differential)
      Number of IOs using ODDR/TDDR:           8 (4 differential)
      Number of IOs using IDDR/ODDR/TDDR:     32 (0 differential)
   Number of Block RAMs:          52 out of 208 (25%)
   Number of Large RAMs:          2 out of 7 (29%)
   Number of Logical DSP Functions:
      Number of Pre-Adders (9+9):    0 out of 312 (0%)
      Number of Multipliers (18x18): 6 out of 156 (4%)
         Number of 9X9:        0 (1 18x18 = 2   9x9)
         Number of 18x18:      2 (1 18x18 = 1 18x18)
         Number of 18x36:      2 (2 18x18 = 1 18x36)
         Number of 36x36:      0 (4 18x18 = 1 36x36)
      Number of 54-bit Accumulators: 0 out of 78 (0%)
      Number of 18-bit Registers:    2 out of 312 (1%)
   Number of Physical DSP Components:
      Number of PREADD9:             12 out of 312 (4%)
         Used PREADD9:               0
         Bypassed PREADD9:           12
      Number of MULT9:               12 out of 312 (4%)
         Used MULT9:                 12
         Bypassed MULT9:             0
      Number of MULT18:              6 out of 156 (4%)
         Used MULT18:                6
         Disabled MULT18:            0
      Number of MULT18X36:           2 out of 78 (3%)
         Used MULT18X36:             2
         Disabled MULT18X36:         0
      Number of MULT36:              0 out of 39 (0%)
      Number of ACC54:               0 out of 78 (0%)
      Number of REG18:               10 out of 312 (3%)
         Used REG18:                 2
         Bypassed REG18:             8
   Number of ALUREGs:             0 out of 1 (0%)
   Number of PLLs:                2 out of 4 (50%)
   Number of DDRDLLs:             1 out of 2 (50%)
   Number of DLLDELs:             0 out of 10 (0%)
   Number of DQSs:                4 out of 11 (36%)
   Number of DCSs:                0 out of 2 (0%)
   Number of DCCs:                1 out of 62 (2%)
   Number of PCLKDIVs:            0 out of 2 (0%)
   Number of ECLKDIVs:            1 out of 12 (8%)
   Number of ECLKSYNCs:           1 out of 12 (8%)
   Number of ADC Blocks:          0 out of 1 (0%)
   Number of SGMIICDRs:           0 out of 2 (0%)
   Number of PMUs:                0 out of 1 (0%)
   Number of BNKREF18s:           0 out of 3 (0%)
   Number of BNKREF33s:           0 out of 5 (0%)
   Number of I2CFIFOs:            0 out of 1 (0%)
   Number of Oscillator:          1 out of 1 (100%)
   Number of GSR:                 0 out of 1 (0%)
   Number of Cryptographic Block: 0 out of 1 (0%)
   Number of Config IP:           0 out of 1 (0%)
                 TSALL:           0 out of 1 (0%)
   Number of JTAG:                1 out of 1 (100%)
   Number of Config LMMI:         0 out of 1 (0%)
   Number of Config MULTIBOOT:    0 out of 1 (0%)
   Number of SED:                 0 out of 1 (0%)
   Number of Config WDT:          0 out of 1 (0%)
   Number of PCSs:                0 out of 2 (0%)
   Number of PCIE Link Layers:    0 out of 1 (0%)
   Number of Clocks:  21
      Net pll0_inst_clkop_o_net: 13849 loads, 13849 rising, 0 falling (Driver:
     Pin pll0_inst.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP)
      Net secured_signal_29518: 63 loads, 5 rising, 58 falling (Driver: Pin
     secured_comp_18355/JTCK)
      Net secured_signal_29549: 83 loads, 82 rising, 1 falling (Driver: Pin
     secured_comp_18314/CLKO)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.sclk_o: 6972 loads, 6972 rising, 0
     falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync
     .u0_ECLKDIV.ECLKDIV_inst/DIVOUT)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w: 55 loads, 55
     rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u1_
     clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w: 1 loads, 1 rising, 0
     falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_
     refclk_mon.u_PLL.PLL_inst/CLKOS)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[2]: 9
     loads, 9 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[2].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW270)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[3]: 9
     loads, 9 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[3].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW270)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[0]: 9
     loads, 9 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[0].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW270)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[1]: 9
     loads, 9 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[1].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW270)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[2]: 8
     loads, 8 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[2].VREF.u0_DQSBUF.DQSBUFA_inst/DQSR90)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[3]: 8
     loads, 8 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[3].VREF.u0_DQSBUF.DQSBUFA_inst/DQSR90)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[1]: 8
     loads, 8 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[1].VREF.u0_DQSBUF.DQSBUFA_inst/DQSR90)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[0]: 8
     loads, 8 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[0].VREF.u0_DQSBUF.DQSBUFA_inst/DQSR90)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[3]: 1
     loads, 1 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[3].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[2]: 1
     loads, 1 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[2].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[0]: 1
     loads, 1 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[0].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW)
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[1]: 1
     loads, 1 rising, 0 falling (Driver: Pin lpddr4_inst.lscc_lpddr4_mc_inst.u_l
     p4mem.u_dq_dqs_dm.DQSBUF[1].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW)
      Net ddr_pll_refclk_i_c: 1 loads, 1 rising, 0 falling (Driver: Port
     ddr_pll_refclk_i)
      Net osc0_inst_hf_clk_out_o_net: 1 loads, 1 rising, 0 falling (Driver: Pin
     osc0_inst.lscc_osc_inst.gen_osca.u_OSC_A.OSCA_inst/HFCLKOUT)
      Net secured_signal_67696: 346 loads, 228 rising, 118 falling (Driver: Pin
     secured_comp_50794/Z)
   Number of Clock Enables:  797
      Net VCC: 46 loads, 0 SLICEs
      Net axi2apb0_inst_APB3_M_interconnect_PSELx: 3 loads, 3 SLICEs
      Net secured_signal_184: 2 loads, 2 SLICEs
      Net secured_signal_237: 1 loads, 1 SLICEs
      Net secured_signal_238: 1 loads, 1 SLICEs
      Net secured_signal_257: 32 loads, 32 SLICEs
      Net secured_signal_258: 1 loads, 1 SLICEs
      Net secured_signal_259: 6 loads, 6 SLICEs
      Net secured_signal_356: 1 loads, 1 SLICEs
      Net secured_signal_565: 32 loads, 32 SLICEs
      Net secured_signal_611: 2 loads, 2 SLICEs
      Net secured_signal_619: 1 loads, 1 SLICEs
      Net secured_signal_647: 1 loads, 1 SLICEs
      Net secured_signal_670: 1 loads, 1 SLICEs
      Net secured_signal_672: 1 loads, 1 SLICEs
      Net secured_signal_676: 1 loads, 1 SLICEs
      Net secured_signal_680: 32 loads, 32 SLICEs
      Net secured_signal_693: 1 loads, 1 SLICEs
      Net secured_signal_694: 1 loads, 1 SLICEs
      Net secured_signal_707: 32 loads, 32 SLICEs
      Net secured_signal_928: 2 loads, 2 SLICEs
      Net secured_signal_1067: 1 loads, 1 SLICEs
      Net secured_signal_1070: 1 loads, 1 SLICEs
      Net secured_signal_1171: 1 loads, 1 SLICEs
      Net secured_signal_1172: 32 loads, 32 SLICEs
      Net secured_signal_1194: 1 loads, 1 SLICEs
      Net secured_signal_1199: 32 loads, 32 SLICEs
      Net secured_signal_1320: 32 loads, 32 SLICEs
      Net secured_signal_1322: 31 loads, 31 SLICEs
      Net secured_signal_1333: 2 loads, 2 SLICEs
      Net secured_signal_1334: 32 loads, 32 SLICEs
      Net secured_signal_1336: 1 loads, 1 SLICEs
      Net secured_signal_1361: 1 loads, 1 SLICEs
      Net secured_signal_1364: 1 loads, 1 SLICEs
      Net secured_signal_1432: 1 loads, 1 SLICEs
      Net secured_signal_1433: 1 loads, 1 SLICEs
      Net secured_signal_1438: 1 loads, 1 SLICEs
      Net secured_signal_1439: 1 loads, 1 SLICEs
      Net secured_signal_1450: 1 loads, 1 SLICEs
      Net secured_signal_1463: 1 loads, 1 SLICEs
      Net secured_signal_1933: 37 loads, 37 SLICEs
      Net secured_signal_2269: 2 loads, 2 SLICEs
      Net secured_signal_2994: 36 loads, 36 SLICEs
      Net secured_signal_3007: 1 loads, 1 SLICEs
      Net secured_signal_3067: 37 loads, 37 SLICEs
      Net secured_signal_3304: 33 loads, 33 SLICEs
      Net secured_signal_3600: 2 loads, 2 SLICEs
      Net secured_signal_3601: 1 loads, 1 SLICEs
      Net secured_signal_3602: 1 loads, 1 SLICEs
      Net secured_signal_3620: 35 loads, 35 SLICEs
      Net secured_signal_4257: 2 loads, 2 SLICEs
      Net secured_signal_4260: 33 loads, 33 SLICEs
      Net secured_signal_4295: 1 loads, 1 SLICEs
      Net secured_signal_4302: 1 loads, 1 SLICEs
      Net secured_signal_4323: 27 loads, 27 SLICEs
      Net secured_signal_5124: 35 loads, 35 SLICEs
      Net secured_signal_5694: 1 loads, 1 SLICEs
      Net secured_signal_5697: 1 loads, 1 SLICEs
      Net secured_signal_5749: 2 loads, 2 SLICEs
      Net secured_signal_5787: 5 loads, 5 SLICEs
      Net secured_signal_5842: 5 loads, 5 SLICEs
      Net secured_signal_5867: 2 loads, 2 SLICEs
      Net secured_signal_5886: 2 loads, 2 SLICEs
      Net secured_signal_5894: 2 loads, 2 SLICEs
      Net secured_signal_5897: 2 loads, 2 SLICEs
      Net secured_signal_5982: 260 loads, 260 SLICEs
      Net secured_signal_5983: 1 loads, 1 SLICEs
      Net secured_signal_6474: 5 loads, 5 SLICEs
      Net secured_signal_6776: 1 loads, 1 SLICEs
      Net secured_signal_6780: 260 loads, 260 SLICEs
      Net secured_signal_7275: 5 loads, 5 SLICEs
      Net secured_signal_7505: 1 loads, 1 SLICEs
      Net secured_signal_7506: 1 loads, 1 SLICEs
      Net secured_signal_7513: 1 loads, 1 SLICEs
      Net secured_signal_7514: 1 loads, 1 SLICEs
      Net secured_signal_7521: 1 loads, 1 SLICEs
      Net secured_signal_7522: 1 loads, 1 SLICEs
      Net secured_signal_7527: 1 loads, 1 SLICEs
      Net secured_signal_7528: 1 loads, 1 SLICEs
      Net secured_signal_7534: 1 loads, 1 SLICEs
      Net secured_signal_7535: 1 loads, 1 SLICEs
      Net secured_signal_7550: 1 loads, 1 SLICEs
      Net secured_signal_7554: 20 loads, 20 SLICEs
      Net secured_signal_7557: 1 loads, 1 SLICEs
      Net secured_signal_7589: 1 loads, 1 SLICEs
      Net secured_signal_7593: 1 loads, 1 SLICEs
      Net secured_signal_7600: 1 loads, 1 SLICEs
      Net secured_signal_7605: 2 loads, 2 SLICEs
      Net secured_signal_7621: 1 loads, 1 SLICEs
      Net secured_signal_7624: 38 loads, 38 SLICEs
      Net secured_signal_7628: 1 loads, 1 SLICEs
      Net secured_signal_7676: 1 loads, 1 SLICEs
      Net secured_signal_7677: 37 loads, 37 SLICEs
      Net secured_signal_7686: 1 loads, 1 SLICEs
      Net secured_signal_7692: 1 loads, 1 SLICEs
      Net secured_signal_7739: 1 loads, 1 SLICEs
      Net secured_signal_7740: 36 loads, 36 SLICEs
      Net secured_signal_7749: 1 loads, 1 SLICEs
      Net secured_signal_7755: 1 loads, 1 SLICEs
      Net secured_signal_7802: 2 loads, 2 SLICEs
      Net secured_signal_7846: 36 loads, 36 SLICEs
      Net secured_signal_7887: 2 loads, 2 SLICEs
      Net secured_signal_8015: 2 loads, 2 SLICEs
      Net secured_signal_8016: 36 loads, 36 SLICEs
      Net secured_signal_8116: 36 loads, 36 SLICEs
      Net secured_signal_8144: 2 loads, 2 SLICEs
      Net secured_signal_8227: 36 loads, 36 SLICEs
      Net secured_signal_8269: 2 loads, 2 SLICEs
      Net secured_signal_8320: 1 loads, 1 SLICEs
      Net secured_signal_8321: 1 loads, 1 SLICEs
      Net secured_signal_8322: 257 loads, 257 SLICEs
      Net secured_signal_8323: 257 loads, 257 SLICEs
      Net secured_signal_8330: 1 loads, 1 SLICEs
      Net secured_signal_8332: 1 loads, 1 SLICEs
      Net secured_signal_8594: 1 loads, 1 SLICEs
      Net secured_signal_8596: 1 loads, 1 SLICEs
      Net secured_signal_8599: 33 loads, 33 SLICEs
      Net secured_signal_8601: 33 loads, 33 SLICEs
      Net secured_signal_8606: 1 loads, 1 SLICEs
      Net secured_signal_8608: 1 loads, 1 SLICEs
      Net secured_signal_8648: 1 loads, 1 SLICEs
      Net secured_signal_8650: 1 loads, 1 SLICEs
      Net secured_signal_8653: 33 loads, 33 SLICEs
      Net secured_signal_8661: 1 loads, 1 SLICEs
      Net secured_signal_8662: 33 loads, 33 SLICEs
      Net secured_signal_8665: 1 loads, 1 SLICEs
      Net secured_signal_8706: 1 loads, 1 SLICEs
      Net secured_signal_8707: 1 loads, 1 SLICEs
      Net secured_signal_8717: 1 loads, 1 SLICEs
      Net secured_signal_8718: 1 loads, 1 SLICEs
      Net secured_signal_8726: 33 loads, 33 SLICEs
      Net secured_signal_8728: 33 loads, 33 SLICEs
      Net secured_signal_8729: 1 loads, 1 SLICEs
      Net secured_signal_8730: 1 loads, 1 SLICEs
      Net secured_signal_8738: 1 loads, 1 SLICEs
      Net secured_signal_8741: 1 loads, 1 SLICEs
      Net secured_signal_8786: 37 loads, 37 SLICEs
      Net secured_signal_8790: 1 loads, 1 SLICEs
      Net secured_signal_8833: 2 loads, 2 SLICEs
      Net secured_signal_8887: 39 loads, 39 SLICEs
      Net secured_signal_8891: 1 loads, 1 SLICEs
      Net secured_signal_8940: 2 loads, 2 SLICEs
      Net secured_signal_8994: 1 loads, 1 SLICEs
      Net secured_signal_8999: 37 loads, 37 SLICEs
      Net secured_signal_9041: 2 loads, 2 SLICEs
      Net secured_signal_9091: 24 loads, 24 SLICEs
      Net secured_signal_9097: 1 loads, 1 SLICEs
      Net secured_signal_9127: 2 loads, 2 SLICEs
      Net secured_signal_9166: 2 loads, 2 SLICEs
      Net secured_signal_9169: 4 loads, 4 SLICEs
      Net secured_signal_9175: 1 loads, 1 SLICEs
      Net secured_signal_9184: 2 loads, 2 SLICEs
      Net secured_signal_9201: 1 loads, 1 SLICEs
      Net secured_signal_9202: 1 loads, 1 SLICEs
      Net secured_signal_9203: 1 loads, 1 SLICEs
      Net secured_signal_9207: 1 loads, 1 SLICEs
      Net secured_signal_9208: 2 loads, 2 SLICEs
      Net secured_signal_9219: 1 loads, 1 SLICEs
      Net secured_signal_9220: 1 loads, 1 SLICEs
      Net secured_signal_9231: 8 loads, 8 SLICEs
      Net secured_signal_9244: 1 loads, 1 SLICEs
      Net secured_signal_9251: 1 loads, 1 SLICEs
      Net secured_signal_9263: 1 loads, 1 SLICEs
      Net secured_signal_9292: 37 loads, 37 SLICEs
      Net secured_signal_9297: 1 loads, 1 SLICEs
      Net secured_signal_9415: 1 loads, 1 SLICEs
      Net secured_signal_9416: 37 loads, 37 SLICEs
      Net secured_signal_9417: 2 loads, 2 SLICEs
      Net secured_signal_9418: 37 loads, 37 SLICEs
      Net secured_signal_9419: 2 loads, 2 SLICEs
      Net secured_signal_9425: 35 loads, 35 SLICEs
      Net secured_signal_9426: 33 loads, 33 SLICEs
      Net secured_signal_9522: 37 loads, 37 SLICEs
      Net secured_signal_10467: 1 loads, 1 SLICEs
      Net secured_signal_10471: 1 loads, 1 SLICEs
      Net secured_signal_10472: 1 loads, 1 SLICEs
      Net secured_signal_10480: 2 loads, 2 SLICEs
      Net secured_signal_10493: 37 loads, 37 SLICEs
      Net secured_signal_10494: 2 loads, 2 SLICEs
      Net secured_signal_10495: 37 loads, 37 SLICEs
      Net secured_signal_10496: 2 loads, 2 SLICEs
      Net secured_signal_10787: 36 loads, 36 SLICEs
      Net secured_signal_11482: 1 loads, 1 SLICEs
      Net secured_signal_11486: 1 loads, 1 SLICEs
      Net secured_signal_11489: 1 loads, 1 SLICEs
      Net secured_signal_11493: 1 loads, 1 SLICEs
      Net secured_signal_11495: 288 loads, 288 SLICEs
      Net secured_signal_11497: 1 loads, 1 SLICEs
      Net secured_signal_11505: 8 loads, 8 SLICEs
      Net secured_signal_11514: 288 loads, 288 SLICEs
      Net secured_signal_11519: 1 loads, 1 SLICEs
      Net secured_signal_11772: 1 loads, 1 SLICEs
      Net secured_signal_11773: 1 loads, 1 SLICEs
      Net secured_signal_11776: 2 loads, 2 SLICEs
      Net secured_signal_11839: 2 loads, 2 SLICEs
      Net secured_signal_11842: 8 loads, 8 SLICEs
      Net secured_signal_12832: 1 loads, 1 SLICEs
      Net secured_signal_13036: 37 loads, 37 SLICEs
      Net secured_signal_13037: 2 loads, 2 SLICEs
      Net secured_signal_13038: 37 loads, 37 SLICEs
      Net secured_signal_13039: 2 loads, 2 SLICEs
      Net secured_signal_14167: 1 loads, 1 SLICEs
      Net secured_signal_14215: 37 loads, 37 SLICEs
      Net secured_signal_14216: 2 loads, 2 SLICEs
      Net secured_signal_14217: 37 loads, 37 SLICEs
      Net secured_signal_14218: 2 loads, 2 SLICEs
      Net secured_signal_14223: 289 loads, 289 SLICEs
      Net secured_signal_14238: 37 loads, 37 SLICEs
      Net secured_signal_14244: 37 loads, 37 SLICEs
      Net secured_signal_14416: 1 loads, 1 SLICEs
      Net secured_signal_14542: 259 loads, 259 SLICEs
      Net secured_signal_20348: 260 loads, 260 SLICEs
      Net secured_signal_25185: 1 loads, 1 SLICEs
      Net secured_signal_25194: 1 loads, 1 SLICEs
      Net secured_signal_25208: 1 loads, 1 SLICEs
      Net secured_signal_25238: 24 loads, 24 SLICEs
      Net secured_signal_25242: 1 loads, 1 SLICEs
      Net secured_signal_25360: 1 loads, 1 SLICEs
      Net secured_signal_25361: 24 loads, 24 SLICEs
      Net secured_signal_25362: 2 loads, 2 SLICEs
      Net secured_signal_25363: 24 loads, 24 SLICEs
      Net secured_signal_25364: 2 loads, 2 SLICEs
      Net secured_signal_25370: 35 loads, 35 SLICEs
      Net secured_signal_25371: 37 loads, 37 SLICEs
      Net secured_signal_25465: 21 loads, 21 SLICEs
      Net secured_signal_26349: 1 loads, 1 SLICEs
      Net secured_signal_26353: 1 loads, 1 SLICEs
      Net secured_signal_26354: 1 loads, 1 SLICEs
      Net secured_signal_26364: 2 loads, 2 SLICEs
      Net secured_signal_26378: 21 loads, 21 SLICEs
      Net secured_signal_26379: 2 loads, 2 SLICEs
      Net secured_signal_26380: 21 loads, 21 SLICEs
      Net secured_signal_26381: 2 loads, 2 SLICEs
      Net secured_signal_26590: 36 loads, 36 SLICEs
      Net secured_signal_27329: 1 loads, 1 SLICEs
      Net secured_signal_27338: 35 loads, 35 SLICEs
      Net secured_signal_27341: 1 loads, 1 SLICEs
      Net secured_signal_27342: 1 loads, 1 SLICEs
      Net secured_signal_27354: 1 loads, 1 SLICEs
      Net secured_signal_27383: 39 loads, 39 SLICEs
      Net secured_signal_27389: 1 loads, 1 SLICEs
      Net secured_signal_27503: 39 loads, 39 SLICEs
      Net secured_signal_27504: 2 loads, 2 SLICEs
      Net secured_signal_27505: 39 loads, 39 SLICEs
      Net secured_signal_27506: 2 loads, 2 SLICEs
      Net secured_signal_27510: 33 loads, 33 SLICEs
      Net secured_signal_27606: 39 loads, 39 SLICEs
      Net secured_signal_28561: 1 loads, 1 SLICEs
      Net secured_signal_28565: 1 loads, 1 SLICEs
      Net secured_signal_28566: 1 loads, 1 SLICEs
      Net secured_signal_28574: 2 loads, 2 SLICEs
      Net secured_signal_28587: 39 loads, 39 SLICEs
      Net secured_signal_28588: 2 loads, 2 SLICEs
      Net secured_signal_28589: 39 loads, 39 SLICEs
      Net secured_signal_28590: 2 loads, 2 SLICEs
      Net secured_signal_28891: 36 loads, 36 SLICEs
      Net secured_signal_29514: 2 loads, 2 SLICEs
      Net secured_signal_29524: 1 loads, 1 SLICEs
      Net secured_signal_29530: 1 loads, 1 SLICEs
      Net secured_signal_29532: 2 loads, 2 SLICEs
      Net secured_signal_29581: 23 loads, 23 SLICEs
      Net secured_signal_29642: 17 loads, 17 SLICEs
      Net secured_signal_29671: 4 loads, 4 SLICEs
      Net secured_signal_29691: 4 loads, 4 SLICEs
      Net secured_signal_29692: 1 loads, 1 SLICEs
      Net secured_signal_29696: 2 loads, 2 SLICEs
      Net secured_signal_29699: 32 loads, 32 SLICEs
      Net secured_signal_29706: 34 loads, 34 SLICEs
      Net secured_signal_29826: 2 loads, 2 SLICEs
      Net secured_signal_29838: 32 loads, 32 SLICEs
      Net secured_signal_29909: 1 loads, 1 SLICEs
      Net secured_signal_29911: 1 loads, 1 SLICEs
      Net secured_signal_29917: 8 loads, 8 SLICEs
      Net secured_signal_29918: 65 loads, 65 SLICEs
      Net secured_signal_30037: 3 loads, 3 SLICEs
      Net secured_signal_30039: 3 loads, 3 SLICEs
      Net secured_signal_30041: 3 loads, 3 SLICEs
      Net secured_signal_30043: 3 loads, 3 SLICEs
      Net secured_signal_30045: 32 loads, 32 SLICEs
      Net secured_signal_30072: 2 loads, 2 SLICEs
      Net secured_signal_30102: 4 loads, 4 SLICEs
      Net secured_signal_30103: 1 loads, 1 SLICEs
      Net secured_signal_30105: 1 loads, 1 SLICEs
      Net secured_signal_30107: 1 loads, 1 SLICEs
      Net secured_signal_30109: 1 loads, 1 SLICEs
      Net secured_signal_30130: 32 loads, 32 SLICEs
      Net secured_signal_30156: 1 loads, 1 SLICEs
      Net secured_signal_30186: 4 loads, 4 SLICEs
      Net secured_signal_30207: 2 loads, 2 SLICEs
      Net secured_signal_30307: 5 loads, 5 SLICEs
      Net secured_signal_30453: 32 loads, 32 SLICEs
      Net secured_signal_30457: 2 loads, 2 SLICEs
      Net secured_signal_30458: 36 loads, 36 SLICEs
      Net secured_signal_30461: 1 loads, 1 SLICEs
      Net secured_signal_30466: 149 loads, 143 SLICEs
      Net secured_signal_30467: 2 loads, 2 SLICEs
      Net secured_signal_30483: 3 loads, 3 SLICEs
      Net secured_signal_30820: 1 loads, 1 SLICEs
      Net secured_signal_30821: 31 loads, 31 SLICEs
      Net secured_signal_30823: 1 loads, 1 SLICEs
      Net secured_signal_30830: 1 loads, 1 SLICEs
      Net secured_signal_30839: 1 loads, 1 SLICEs
      Net secured_signal_30840: 1 loads, 1 SLICEs
      Net secured_signal_30855: 5 loads, 5 SLICEs
      Net secured_signal_30896: 2 loads, 2 SLICEs
      Net secured_signal_30897: 16 loads, 16 SLICEs
      Net secured_signal_30905: 3 loads, 3 SLICEs
      Net secured_signal_30908: 3 loads, 3 SLICEs
      Net secured_signal_30910: 36 loads, 36 SLICEs
      Net secured_signal_30911: 36 loads, 36 SLICEs
      Net secured_signal_30913: 36 loads, 36 SLICEs
      Net secured_signal_30915: 10 loads, 10 SLICEs
      Net secured_signal_31091: 2 loads, 0 SLICEs
      Net secured_signal_31096: 32 loads, 32 SLICEs
      Net secured_signal_31099: 1 loads, 1 SLICEs
      Net secured_signal_31101: 1 loads, 1 SLICEs
      Net secured_signal_31109: 1 loads, 1 SLICEs
      Net secured_signal_31111: 34 loads, 34 SLICEs
      Net secured_signal_31112: 1 loads, 1 SLICEs
      Net secured_signal_31115: 1 loads, 1 SLICEs
      Net secured_signal_31121: 8 loads, 8 SLICEs
      Net secured_signal_31123: 6 loads, 6 SLICEs
      Net secured_signal_31125: 1 loads, 1 SLICEs
      Net secured_signal_31127: 13 loads, 13 SLICEs
      Net secured_signal_31129: 3 loads, 3 SLICEs
      Net secured_signal_31132: 32 loads, 32 SLICEs
      Net secured_signal_31134: 32 loads, 32 SLICEs
      Net secured_signal_31135: 30 loads, 30 SLICEs
      Net secured_signal_31137: 1 loads, 1 SLICEs
      Net secured_signal_31138: 32 loads, 32 SLICEs
      Net secured_signal_31140: 30 loads, 30 SLICEs
      Net secured_signal_31143: 3 loads, 3 SLICEs
      Net secured_signal_31225: 1 loads, 1 SLICEs
      Net secured_signal_31230: 1 loads, 1 SLICEs
      Net secured_signal_31240: 2 loads, 0 SLICEs
      Net secured_signal_31248: 38 loads, 38 SLICEs
      Net secured_signal_31336: 175 loads, 175 SLICEs
      Net secured_signal_31363: 1 loads, 1 SLICEs
      Net secured_signal_31364: 1 loads, 1 SLICEs
      Net secured_signal_31370: 372 loads, 368 SLICEs
      Net secured_signal_31443: 2 loads, 2 SLICEs
      Net secured_signal_32040: 36 loads, 36 SLICEs
      Net secured_signal_32308: 32 loads, 32 SLICEs
      Net secured_signal_32771: 1 loads, 1 SLICEs
      Net secured_signal_32956: 1 loads, 1 SLICEs
      Net secured_signal_32985: 32 loads, 32 SLICEs
      Net secured_signal_33126: 1 loads, 1 SLICEs
      Net secured_signal_33127: 1 loads, 1 SLICEs
      Net secured_signal_33136: 32 loads, 32 SLICEs
      Net secured_signal_33140: 32 loads, 32 SLICEs
      Net secured_signal_33156: 32 loads, 32 SLICEs
      Net secured_signal_33157: 32 loads, 32 SLICEs
      Net secured_signal_33158: 32 loads, 32 SLICEs
      Net secured_signal_33159: 32 loads, 32 SLICEs
      Net secured_signal_35382: 1 loads, 1 SLICEs
      Net secured_signal_35407: 32 loads, 32 SLICEs
      Net secured_signal_36590: 1 loads, 1 SLICEs
      Net secured_signal_36592: 1 loads, 1 SLICEs
      Net secured_signal_36660: 1 loads, 1 SLICEs
      Net secured_signal_36662: 1 loads, 0 SLICEs
      Net secured_signal_36663: 1 loads, 0 SLICEs
      Net secured_signal_36783: 1 loads, 0 SLICEs
      Net secured_signal_36784: 1 loads, 0 SLICEs
      Net secured_signal_36788: 1 loads, 1 SLICEs
      Net secured_signal_36851: 1 loads, 1 SLICEs
      Net secured_signal_36867: 1 loads, 1 SLICEs
      Net secured_signal_36871: 1 loads, 0 SLICEs
      Net secured_signal_36872: 1 loads, 0 SLICEs
      Net secured_signal_36874: 1 loads, 0 SLICEs
      Net secured_signal_36875: 1 loads, 0 SLICEs
      Net secured_signal_36878: 1 loads, 1 SLICEs
      Net secured_signal_37036: 10 loads, 0 SLICEs
      Net secured_signal_37047: 252 loads, 252 SLICEs
      Net secured_signal_37067: 1 loads, 1 SLICEs
      Net secured_signal_37102: 1 loads, 0 SLICEs
      Net secured_signal_37103: 1 loads, 0 SLICEs
      Net secured_signal_37109: 1 loads, 0 SLICEs
      Net secured_signal_37110: 1 loads, 0 SLICEs
      Net secured_signal_37127: 1 loads, 0 SLICEs
      Net secured_signal_37128: 1 loads, 0 SLICEs
      Net secured_signal_37132: 5 loads, 5 SLICEs
      Net secured_signal_37540: 32 loads, 32 SLICEs
      Net secured_signal_37554: 7 loads, 7 SLICEs
      Net secured_signal_37707: 3 loads, 3 SLICEs
      Net secured_signal_40228: 8 loads, 8 SLICEs
      Net secured_signal_40229: 8 loads, 8 SLICEs
      Net secured_signal_40244: 8 loads, 8 SLICEs
      Net secured_signal_40245: 8 loads, 8 SLICEs
      Net secured_signal_40251: 3 loads, 3 SLICEs
      Net secured_signal_40252: 7 loads, 7 SLICEs
      Net secured_signal_40348: 1 loads, 1 SLICEs
      Net secured_signal_40356: 1 loads, 1 SLICEs
      Net secured_signal_40365: 1 loads, 1 SLICEs
      Net secured_signal_40393: 8 loads, 8 SLICEs
      Net secured_signal_40394: 4 loads, 4 SLICEs
      Net secured_signal_40468: 1 loads, 1 SLICEs
      Net secured_signal_40470: 1 loads, 1 SLICEs
      Net secured_signal_40508: 12 loads, 12 SLICEs
      Net secured_signal_40530: 17 loads, 17 SLICEs
      Net secured_signal_40540: 9 loads, 9 SLICEs
      Net secured_signal_40590: 1 loads, 1 SLICEs
      Net secured_signal_40632: 1 loads, 1 SLICEs
      Net secured_signal_40797: 64 loads, 64 SLICEs
      Net secured_signal_40798: 1 loads, 1 SLICEs
      Net secured_signal_40841: 11 loads, 11 SLICEs
      Net secured_signal_41097: 8 loads, 8 SLICEs
      Net secured_signal_41099: 8 loads, 8 SLICEs
      Net secured_signal_41101: 8 loads, 8 SLICEs
      Net secured_signal_41103: 8 loads, 8 SLICEs
      Net secured_signal_41105: 8 loads, 8 SLICEs
      Net secured_signal_41107: 8 loads, 8 SLICEs
      Net secured_signal_41109: 8 loads, 8 SLICEs
      Net secured_signal_41111: 8 loads, 8 SLICEs
      Net secured_signal_41113: 8 loads, 8 SLICEs
      Net secured_signal_41114: 8 loads, 8 SLICEs
      Net secured_signal_41115: 8 loads, 8 SLICEs
      Net secured_signal_41116: 8 loads, 8 SLICEs
      Net secured_signal_41117: 8 loads, 8 SLICEs
      Net secured_signal_41118: 8 loads, 8 SLICEs
      Net secured_signal_41119: 8 loads, 8 SLICEs
      Net secured_signal_41120: 8 loads, 8 SLICEs
      Net secured_signal_41201: 2 loads, 2 SLICEs
      Net secured_signal_41206: 1 loads, 1 SLICEs
      Net secured_signal_41266: 32 loads, 32 SLICEs
      Net secured_signal_41530: 3 loads, 3 SLICEs
      Net secured_signal_41532: 2 loads, 2 SLICEs
      Net secured_signal_41533: 3 loads, 3 SLICEs
      Net secured_signal_41535: 3 loads, 3 SLICEs
      Net secured_signal_41546: 3 loads, 3 SLICEs
      Net secured_signal_41647: 1 loads, 1 SLICEs
      Net gpio0_inst.lscc_gpio_inst.genblk1.lscc_gpio_lmmi_0.un1_gpio_out_r22_i:
     8 loads, 8 SLICEs
      Net
     gpio0_inst.lscc_gpio_inst.genblk1.lscc_gpio_lmmi_0.int_type_r_1_sqmuxa: 8
     loads, 8 SLICEs
      Net
     gpio0_inst.lscc_gpio_inst.genblk1.lscc_gpio_lmmi_0.int_method_r_1_sqmuxa: 8
     loads, 8 SLICEs
      Net
     gpio0_inst.lscc_gpio_inst.genblk1.lscc_gpio_lmmi_0.int_enable_r_1_sqmuxa: 8
     loads, 8 SLICEs
      Net
     gpio0_inst.lscc_gpio_inst.genblk1.lscc_gpio_lmmi_0.direction_r_1_sqmuxa: 8
     loads, 8 SLICEs
      Net gpio0_inst.lscc_gpio_inst.genblk2.lscc_apb2lmmi_0.bus_sm_cs[1]: 2
     loads, 2 SLICEs
      Net gpio0_inst.lscc_gpio_inst.genblk2.lscc_apb2lmmi_0.apb_pready_o_RNO: 1
     loads, 1 SLICEs
      Net gpio0_inst.lscc_gpio_inst.genblk2.lscc_apb2lmmi_0.lmmi_offset_nxt_0_sq
     muxa: 12 loads, 12 SLICEs
      Net gpio0_inst.lscc_gpio_inst.genblk2.lscc_apb2lmmi_0.N_1626_i: 8 loads, 8
     SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.srst_n: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.phy_srst_n: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIP
     2R88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIQ
     3R88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIR
     4R88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIS
     5R88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIT
     6R88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIU
     7R88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIV
     8R88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNI0
     AR88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNI1
     BR88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNI2
     CR88: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIA
     2EVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIB
     3EVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIC
     4EVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNID
     5EVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIE
     6EVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIF
     7EVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIG
     8EVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIH
     9EVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNII
     AEVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIJ
     BEVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIB
     4FVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIC
     5FVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNID
     6FVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIE
     7FVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIF
     8FVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIG
     9FVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIH
     AFVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNII
     BFVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIJ
     CFVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIK
     DFVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNIC
     6GVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_wready_r_RNID
     7GVB: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.axi_bid_o5: 1
     loads, 1 SLICEs
      Net
     lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_data_fifo_rd_0: 292
     loads, 292 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_ctrl_fifo_rd:
     39 loads, 39 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.un1_rd_en_i_0: 4
     loads, 4 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.un1_wr_en_i: 4
     loads, 4 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.u_int_fifo.u_fifo
     .rd_fifo_en_w: 7 loads, 7 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.u_rsp_fifo.u_fifo
     .full_r_RNI15NPI: 4 loads, 4 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.u_rsp_fifo.u_fifo
     .un1_rd_en_i: 4 loads, 4 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.un3_sig_data_fifo
     _wr_RNIFTMTH: 32 loads, 32 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.u_rsp_fifo.u_fifo
     .rd_fifo_en_w: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo
     .u_fifo_dc.wr_fifo_en_w: 2 loads, 2 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo
     .u_fifo_dc.wr_fifo_en_w: 4 loads, 4 SLICEs
      Net
     lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.rd_ctrl_fifo_wr_RNO: 1
     loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.axi_rd_outstandin
     g19_1: 41 loads, 41 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.ASYNC.u_ctrl_fifo
     .u_fifo_dc.rd_fifo_en_w: 44 loads, 44 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.ASYNC.u_ctrl_fifo
     .u_fifo_dc.wr_fifo_en_w: 2 loads, 2 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.N_
     69_i: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.rd_rsp_valid: 39 loads, 39 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.en
     able_bus_d: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.en
     able_bus_d_2: 22 loads, 22 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.co
     unte: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.bu
     s_wraddre: 6 loads, 6 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     2_rdata_out_en_rep1: 128 loads, 128 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     2_rdata_out_en_rep2: 128 loads, 128 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_sig_dpram_wr_d_inv_0_i: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_sig_dpram_wr_d_inv_2_i: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_sig_dpram_wr_d_inv_4_i: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_sig_dpram_wr_d_inv_6_i: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_sig_dpram_wr_d_inv_8_i: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_sig_dpram_wr_d_inv_10_i: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_sig_dpram_wr_d_inv_12_i: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_sig_dpram_wr_d_inv_14_i: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.un
     1_enable_bus_dd_1[0]: 2 loads, 2 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.m_rd_done_w: 32 loads, 32
     SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.m_buf1_valid_r_RNO: 1 loads,
     1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.m_buf0_valid_r_RNO: 1 loads,
     1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.s_rdata_valid_w: 32 loads,
     32 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.s_buf0_wr_ok_w: 44 loads, 44
     SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.un2_s_clear_buf0_w: 1 loads,
     1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.s_buf1_wr_ok_w: 44 loads, 44
     SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.un2_s_clear_buf1_w: 1 loads,
     1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.i_apb_cdc.N_1765_i: 44 loads, 44
     SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.s_cdc_psel_w: 2 loads, 2 SLICEs
      Net secured_signal_47774: 1 loads, 1 SLICEs
      Net secured_signal_47780: 1 loads, 1 SLICEs
      Net secured_signal_48890: 1 loads, 1 SLICEs
      Net secured_signal_48893: 25 loads, 25 SLICEs
      Net secured_signal_48895: 25 loads, 25 SLICEs
      Net secured_signal_48897: 25 loads, 25 SLICEs
      Net secured_signal_48899: 25 loads, 25 SLICEs
      Net secured_signal_48904: 25 loads, 25 SLICEs
      Net secured_signal_48906: 25 loads, 25 SLICEs
      Net secured_signal_48908: 25 loads, 25 SLICEs
      Net secured_signal_48910: 25 loads, 25 SLICEs
      Net secured_signal_48925: 19 loads, 19 SLICEs
      Net secured_signal_49032: 1 loads, 1 SLICEs
      Net secured_signal_49037: 3 loads, 3 SLICEs
      Net secured_signal_49040: 3 loads, 3 SLICEs
      Net secured_signal_49070: 1 loads, 1 SLICEs
      Net secured_signal_49071: 1 loads, 1 SLICEs
      Net secured_signal_49073: 1 loads, 1 SLICEs
      Net secured_signal_49075: 1 loads, 1 SLICEs
      Net secured_signal_49077: 16 loads, 16 SLICEs
      Net secured_signal_49079: 16 loads, 16 SLICEs
      Net secured_signal_49080: 24 loads, 24 SLICEs
      Net secured_signal_49081: 24 loads, 24 SLICEs
      Net secured_signal_49083: 16 loads, 16 SLICEs
      Net secured_signal_49084: 24 loads, 24 SLICEs
      Net secured_signal_49393: 1 loads, 1 SLICEs
      Net secured_signal_49394: 1 loads, 1 SLICEs
      Net secured_signal_49398: 1 loads, 1 SLICEs
      Net secured_signal_49731: 3 loads, 3 SLICEs
      Net secured_signal_49733: 3 loads, 3 SLICEs
      Net secured_signal_49735: 1 loads, 1 SLICEs
      Net secured_signal_49754: 1 loads, 1 SLICEs
      Net secured_signal_49756: 1 loads, 1 SLICEs
      Net secured_signal_49758: 3 loads, 3 SLICEs
      Net secured_signal_49760: 1 loads, 1 SLICEs
      Net secured_signal_49778: 3 loads, 3 SLICEs
      Net secured_signal_49781: 3 loads, 3 SLICEs
      Net secured_signal_49784: 3 loads, 3 SLICEs
      Net secured_signal_50132: 1 loads, 1 SLICEs
      Net secured_signal_50133: 1 loads, 1 SLICEs
      Net secured_signal_50134: 1 loads, 1 SLICEs
      Net secured_signal_50135: 1 loads, 1 SLICEs
      Net secured_signal_50137: 24 loads, 24 SLICEs
      Net secured_signal_50464: 1 loads, 1 SLICEs
      Net secured_signal_51586: 1 loads, 1 SLICEs
      Net secured_signal_51589: 1 loads, 1 SLICEs
      Net secured_signal_51592: 24 loads, 24 SLICEs
      Net secured_signal_51593: 16 loads, 16 SLICEs
      Net secured_signal_51594: 1 loads, 1 SLICEs
      Net secured_signal_51597: 1 loads, 1 SLICEs
      Net secured_signal_51600: 19 loads, 19 SLICEs
      Net secured_signal_51602: 1 loads, 1 SLICEs
      Net secured_signal_51603: 19 loads, 19 SLICEs
      Net secured_signal_51605: 1 loads, 1 SLICEs
      Net secured_signal_51606: 24 loads, 24 SLICEs
      Net secured_signal_51607: 24 loads, 24 SLICEs
      Net secured_signal_51609: 1 loads, 1 SLICEs
      Net secured_signal_51611: 3 loads, 3 SLICEs
      Net secured_signal_51634: 24 loads, 24 SLICEs
      Net secured_signal_51635: 19 loads, 19 SLICEs
      Net secured_signal_51637: 1 loads, 1 SLICEs
      Net secured_signal_52023: 5 loads, 5 SLICEs
      Net secured_signal_52031: 1 loads, 1 SLICEs
      Net secured_signal_52599: 5 loads, 5 SLICEs
      Net secured_signal_52602: 1 loads, 1 SLICEs
      Net secured_signal_52991: 5 loads, 5 SLICEs
      Net secured_signal_52994: 1 loads, 1 SLICEs
      Net secured_signal_53398: 5 loads, 5 SLICEs
      Net secured_signal_53401: 1 loads, 1 SLICEs
      Net secured_signal_53793: 3 loads, 3 SLICEs
      Net secured_signal_53798: 1 loads, 1 SLICEs
      Net secured_signal_54305: 3 loads, 3 SLICEs
      Net secured_signal_54311: 1 loads, 1 SLICEs
      Net secured_signal_54677: 3 loads, 3 SLICEs
      Net secured_signal_54683: 1 loads, 1 SLICEs
      Net secured_signal_55056: 3 loads, 3 SLICEs
      Net secured_signal_55060: 1 loads, 1 SLICEs
      Net secured_signal_55317: 9 loads, 9 SLICEs
      Net secured_signal_55464: 9 loads, 9 SLICEs
      Net secured_signal_55465: 7 loads, 7 SLICEs
      Net secured_signal_55471: 10 loads, 10 SLICEs
      Net secured_signal_55607: 7 loads, 7 SLICEs
      Net secured_signal_55927: 6 loads, 6 SLICEs
      Net secured_signal_55984: 1 loads, 1 SLICEs
      Net secured_signal_55985: 1 loads, 1 SLICEs
      Net secured_signal_55986: 1 loads, 1 SLICEs
      Net secured_signal_55987: 1 loads, 1 SLICEs
      Net secured_signal_55988: 1 loads, 1 SLICEs
      Net secured_signal_55989: 1 loads, 1 SLICEs
      Net secured_signal_55990: 1 loads, 1 SLICEs
      Net secured_signal_55991: 1 loads, 1 SLICEs
      Net secured_signal_56027: 1 loads, 1 SLICEs
      Net secured_signal_56060: 8 loads, 8 SLICEs
      Net secured_signal_56601: 1 loads, 1 SLICEs
      Net secured_signal_56602: 1 loads, 1 SLICEs
      Net secured_signal_56664: 14 loads, 14 SLICEs
      Net secured_signal_56809: 1 loads, 1 SLICEs
      Net secured_signal_56811: 1 loads, 1 SLICEs
      Net secured_signal_56943: 4 loads, 4 SLICEs
      Net secured_signal_56944: 4 loads, 4 SLICEs
      Net secured_signal_58383: 1 loads, 1 SLICEs
      Net secured_signal_58386: 1 loads, 1 SLICEs
      Net secured_signal_58388: 1 loads, 1 SLICEs
      Net secured_signal_58472: 5 loads, 5 SLICEs
      Net secured_signal_58549: 8 loads, 8 SLICEs
      Net secured_signal_58555: 8 loads, 8 SLICEs
      Net secured_signal_58648: 32 loads, 32 SLICEs
      Net secured_signal_58650: 12 loads, 12 SLICEs
      Net secured_signal_58681: 32 loads, 32 SLICEs
      Net secured_signal_58691: 12 loads, 12 SLICEs
      Net secured_signal_58865: 2 loads, 2 SLICEs
      Net secured_signal_58871: 1 loads, 1 SLICEs
      Net secured_signal_59003: 34 loads, 34 SLICEs
      Net secured_signal_59011: 31 loads, 31 SLICEs
      Net secured_signal_59012: 1 loads, 1 SLICEs
      Net secured_signal_59013: 5 loads, 5 SLICEs
      Net secured_signal_59014: 1 loads, 1 SLICEs
      Net secured_signal_59016: 1 loads, 1 SLICEs
      Net secured_signal_59018: 1 loads, 1 SLICEs
      Net secured_signal_59026: 5 loads, 5 SLICEs
      Net secured_signal_59310: 30 loads, 30 SLICEs
      Net secured_signal_59314: 2 loads, 2 SLICEs
      Net secured_signal_59318: 2 loads, 2 SLICEs
      Net secured_signal_59351: 60 loads, 60 SLICEs
      Net secured_signal_59372: 199 loads, 199 SLICEs
      Net secured_signal_59666: 48 loads, 48 SLICEs
      Net secured_signal_59678: 4 loads, 4 SLICEs
      Net secured_signal_59864: 3 loads, 3 SLICEs
      Net secured_signal_59944: 1 loads, 1 SLICEs
      Net secured_signal_60323: 30 loads, 30 SLICEs
      Net secured_signal_60324: 1 loads, 1 SLICEs
      Net secured_signal_61046: 1 loads, 1 SLICEs
      Net secured_signal_61047: 4 loads, 4 SLICEs
      Net secured_signal_61096: 16 loads, 0 SLICEs
      Net secured_signal_61133: 16 loads, 0 SLICEs
      Net secured_signal_61188: 10 loads, 10 SLICEs
      Net secured_signal_61190: 2 loads, 2 SLICEs
      Net secured_signal_61192: 7 loads, 7 SLICEs
      Net secured_signal_61193: 9 loads, 9 SLICEs
      Net secured_signal_61195: 1 loads, 1 SLICEs
      Net secured_signal_61197: 1 loads, 1 SLICEs
      Net secured_signal_61199: 1 loads, 1 SLICEs
      Net secured_signal_61201: 1 loads, 1 SLICEs
      Net secured_signal_61203: 5 loads, 5 SLICEs
      Net secured_signal_61506: 12 loads, 12 SLICEs
      Net secured_signal_61507: 1 loads, 1 SLICEs
      Net secured_signal_61598: 7 loads, 7 SLICEs
      Net secured_signal_61736: 10 loads, 10 SLICEs
      Net secured_signal_61737: 18 loads, 18 SLICEs
      Net secured_signal_61738: 5 loads, 5 SLICEs
      Net secured_signal_61739: 7 loads, 7 SLICEs
      Net secured_signal_61740: 2 loads, 2 SLICEs
      Net secured_signal_61741: 25 loads, 25 SLICEs
      Net secured_signal_61749: 16 loads, 16 SLICEs
      Net secured_signal_61750: 16 loads, 16 SLICEs
      Net secured_signal_61762: 32 loads, 32 SLICEs
      Net secured_signal_61763: 32 loads, 32 SLICEs
      Net secured_signal_61878: 16 loads, 16 SLICEs
      Net secured_signal_61906: 8 loads, 8 SLICEs
      Net secured_signal_61917: 5 loads, 5 SLICEs
      Net secured_signal_61964: 4 loads, 4 SLICEs
      Net secured_signal_61965: 4 loads, 4 SLICEs
      Net secured_signal_61966: 4 loads, 4 SLICEs
      Net secured_signal_61967: 4 loads, 4 SLICEs
      Net secured_signal_62807: 4 loads, 4 SLICEs
      Net secured_signal_62954: 3 loads, 3 SLICEs
      Net secured_signal_62957: 4 loads, 4 SLICEs
      Net secured_signal_62959: 4 loads, 4 SLICEs
      Net secured_signal_62998: 1 loads, 1 SLICEs
      Net secured_signal_63004: 18 loads, 18 SLICEs
      Net secured_signal_63007: 1 loads, 1 SLICEs
      Net secured_signal_63102: 28 loads, 28 SLICEs
      Net secured_signal_63104: 28 loads, 28 SLICEs
      Net secured_signal_64737: 5 loads, 5 SLICEs
      Net secured_signal_65258: 288 loads, 288 SLICEs
      Net secured_signal_66375: 26 loads, 26 SLICEs
      Net secured_signal_66583: 7 loads, 7 SLICEs
      Net secured_signal_66584: 7 loads, 7 SLICEs
      Net secured_signal_67020: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.un1_sync_clk_update_2: 1
     loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u1_mem_sync.un1
     _freeze2init_0_sqmuxa_1: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u1_mem_sync.un1
     _ddr_clk_update_rise_4_i: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u1_mem_sync.un1
     _ddr_clk_update_rise_2_i_0: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.CA_GRP_ENA.u_ca_grp.N_73_i: 3
     loads, 3 SLICEs
      Net secured_signal_67698: 4 loads, 4 SLICEs
      Net secured_signal_67803: 1 loads, 1 SLICEs
      Net secured_signal_67829: 64 loads, 64 SLICEs
      Net secured_signal_67831: 1 loads, 1 SLICEs
      Net secured_signal_67880: 32 loads, 32 SLICEs
      Net secured_signal_67952: 1 loads, 1 SLICEs
      Net secured_signal_68012: 1 loads, 1 SLICEs
      Net secured_signal_68394: 1 loads, 1 SLICEs
      Net secured_signal_68397: 3 loads, 3 SLICEs
      Net secured_signal_68399: 8 loads, 8 SLICEs
      Net secured_signal_68401: 8 loads, 8 SLICEs
      Net secured_signal_68404: 11 loads, 11 SLICEs
      Net secured_signal_68414: 32 loads, 32 SLICEs
      Net secured_signal_68416: 32 loads, 32 SLICEs
      Net secured_signal_68418: 32 loads, 32 SLICEs
      Net secured_signal_68421: 1 loads, 1 SLICEs
      Net secured_signal_68423: 32 loads, 32 SLICEs
      Net secured_signal_68835: 5 loads, 5 SLICEs
      Net secured_signal_68902: 10 loads, 10 SLICEs
      Net secured_signal_68905: 1 loads, 1 SLICEs
      Net secured_signal_68913: 8 loads, 8 SLICEs
      Net secured_signal_68915: 8 loads, 8 SLICEs
      Net secured_signal_68917: 8 loads, 8 SLICEs
      Net secured_signal_68919: 8 loads, 8 SLICEs
      Net secured_signal_68921: 8 loads, 8 SLICEs
      Net secured_signal_68923: 8 loads, 8 SLICEs
      Net secured_signal_68925: 8 loads, 8 SLICEs
      Net secured_signal_68927: 8 loads, 8 SLICEs
      Net secured_signal_68929: 8 loads, 8 SLICEs
      Net secured_signal_68931: 8 loads, 8 SLICEs
      Net secured_signal_69001: 8 loads, 8 SLICEs
      Net secured_signal_69003: 8 loads, 8 SLICEs
      Net secured_signal_69004: 8 loads, 8 SLICEs
      Net secured_signal_69005: 1 loads, 1 SLICEs
      Net secured_signal_69006: 1 loads, 1 SLICEs
      Net secured_signal_69007: 1 loads, 1 SLICEs
      Net secured_signal_69008: 1 loads, 1 SLICEs
      Net secured_signal_69010: 16 loads, 16 SLICEs
      Net secured_signal_69012: 16 loads, 16 SLICEs
      Net secured_signal_69014: 4 loads, 4 SLICEs
      Net secured_signal_69016: 8 loads, 8 SLICEs
      Net secured_signal_69087: 11 loads, 11 SLICEs
      Net secured_signal_69253: 32 loads, 32 SLICEs
      Net secured_signal_69264: 1 loads, 1 SLICEs
      Net secured_signal_69266: 1 loads, 1 SLICEs
      Net secured_signal_69268: 1 loads, 1 SLICEs
      Net secured_signal_69269: 32 loads, 32 SLICEs
      Net secured_signal_69270: 1 loads, 1 SLICEs
      Net secured_signal_69300: 3 loads, 3 SLICEs
      Net secured_signal_69367: 35 loads, 35 SLICEs
      Net secured_signal_69385: 32 loads, 32 SLICEs
      Net secured_signal_69406: 32 loads, 32 SLICEs
      Net secured_signal_69490: 1 loads, 1 SLICEs
      Net secured_signal_69493: 2 loads, 2 SLICEs
      Net secured_signal_69634: 8 loads, 8 SLICEs
      Net secured_signal_69693: 1 loads, 1 SLICEs
      Net secured_signal_69741: 8 loads, 8 SLICEs
      Net secured_signal_69831: 32 loads, 32 SLICEs
      Net secured_signal_69936: 8 loads, 8 SLICEs
      Net secured_signal_70214: 1 loads, 1 SLICEs
      Net secured_signal_70220: 1 loads, 1 SLICEs
      Net secured_signal_70274: 1 loads, 1 SLICEs
      Net secured_signal_70395: 68 loads, 68 SLICEs
      Net secured_signal_70398: 32 loads, 32 SLICEs
      Net secured_signal_70400: 1 loads, 1 SLICEs
      Net secured_signal_70403: 64 loads, 64 SLICEs
      Net secured_signal_70405: 64 loads, 64 SLICEs
      Net secured_signal_70407: 5 loads, 5 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.N_68_i: 1
     loads, 1 SLICEs
      Net
     system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.araddr_pipe_r5:
     23 loads, 23 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.axi_awready
     _r_RNI0HVID: 20 loads, 20 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.axi_rlast_r
     _RNO_0: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.wlast_r7:
     36 loads, 36 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.N_32: 32
     loads, 32 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_araddr_
     in_r7_10_i: 32 loads, 32 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.mem_rdata_v
     alid_2r_3_i: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_slv
     err_r8: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.N_1682_i: 9
     loads, 9 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_mem_arl
     en_r6_i: 3 loads, 3 SLICEs
      Net
     system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.awaddr_pipe_r5:
     21 loads, 21 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_bid
     _r7_4_i: 2 loads, 2 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_arpipel
     ine_d110_1_i: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_mem_rad
     dr_prev_r6: 32 loads, 32 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_rre
     ady_i_1: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_awaddr_
     in_r7_1_i: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_mem_arl
     en_r6_2_i_0: 7 loads, 7 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_bva
     lid_r10_4: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_arpipel
     ine_d110_0: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_wva
     lid_i_4: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_bva
     lid_r10_2_i: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_araddr_
     in_r7_3_0: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_araddr_
     in_r7_1_0_0: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_araddr_
     in_r7_5_i_0_0: 24 loads, 24 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_rva
     lid_r12_3_0_0: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.N_75_1: 32
     loads, 32 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_rre
     ady_i: 1 loads, 1 SLICEs
      Net system0_inst.lscc_sys_mem_inst.bridge_s0.genblk1.bridge_s0.un1_axi_bre
     ady_i_2: 1 loads, 1 SLICEs
   Number of LSRs:  126
      Net VCC: 51 loads, 0 SLICEs
      Net equation_module_inst_O_net: 1 loads, 1 SLICEs
      Net cpu_inst_system_resetn_o_net_i: 1 loads, 0 SLICEs
      Net cpu_inst_system_resetn_o_net: 7766 loads, 7752 SLICEs
      Net secured_signal_2376: 10 loads, 10 SLICEs
      Net secured_signal_2404: 1 loads, 1 SLICEs
      Net cpu_inst_AXI_M_DATA_interconnect_ARADDR[21]: 2 loads, 2 SLICEs
      Net secured_signal_2714: 10 loads, 10 SLICEs
      Net secured_signal_2921: 5 loads, 5 SLICEs
      Net secured_signal_3049: 10 loads, 10 SLICEs
      Net secured_signal_3082: 3 loads, 3 SLICEs
      Net secured_signal_3595: 9 loads, 9 SLICEs
      Net secured_signal_4329: 1 loads, 1 SLICEs
      Net secured_signal_4738: 7 loads, 7 SLICEs
      Net secured_signal_5104: 9 loads, 9 SLICEs
      Net secured_signal_7855: 1 loads, 1 SLICEs
      Net secured_signal_7979: 1 loads, 1 SLICEs
      Net secured_signal_8062: 1 loads, 1 SLICEs
      Net secured_signal_8238: 1 loads, 1 SLICEs
      Net secured_signal_9289: 10 loads, 10 SLICEs
      Net secured_signal_9517: 10 loads, 10 SLICEs
      Net secured_signal_9763: 10 loads, 10 SLICEs
      Net secured_signal_9764: 10 loads, 10 SLICEs
      Net secured_signal_9765: 10 loads, 10 SLICEs
      Net secured_signal_9766: 10 loads, 10 SLICEs
      Net secured_signal_10481: 1 loads, 1 SLICEs
      Net secured_signal_11045: 9 loads, 9 SLICEs
      Net secured_signal_11046: 9 loads, 9 SLICEs
      Net secured_signal_11047: 9 loads, 9 SLICEs
      Net secured_signal_11048: 9 loads, 9 SLICEs
      Net secured_signal_11688: 10 loads, 10 SLICEs
      Net secured_signal_11854: 10 loads, 10 SLICEs
      Net secured_signal_15049: 3 loads, 3 SLICEs
      Net secured_signal_15101: 3 loads, 3 SLICEs
      Net secured_signal_15203: 73 loads, 73 SLICEs
      Net secured_signal_15204: 73 loads, 73 SLICEs
      Net secured_signal_15205: 73 loads, 73 SLICEs
      Net secured_signal_15206: 73 loads, 73 SLICEs
      Net secured_signal_20157: 1 loads, 1 SLICEs
      Net secured_signal_21953: 65 loads, 65 SLICEs
      Net secured_signal_21954: 65 loads, 65 SLICEs
      Net secured_signal_21955: 65 loads, 65 SLICEs
      Net secured_signal_21956: 65 loads, 65 SLICEs
      Net secured_signal_25235: 7 loads, 7 SLICEs
      Net secured_signal_25470: 6 loads, 6 SLICEs
      Net secured_signal_25641: 10 loads, 10 SLICEs
      Net secured_signal_25642: 10 loads, 10 SLICEs
      Net secured_signal_25643: 10 loads, 10 SLICEs
      Net secured_signal_25644: 10 loads, 10 SLICEs
      Net secured_signal_26365: 1 loads, 1 SLICEs
      Net secured_signal_26848: 9 loads, 9 SLICEs
      Net secured_signal_26849: 9 loads, 9 SLICEs
      Net secured_signal_26850: 9 loads, 9 SLICEs
      Net secured_signal_26851: 9 loads, 9 SLICEs
      Net secured_signal_27380: 10 loads, 10 SLICEs
      Net secured_signal_27601: 10 loads, 10 SLICEs
      Net secured_signal_27853: 10 loads, 10 SLICEs
      Net secured_signal_27854: 10 loads, 10 SLICEs
      Net secured_signal_27855: 10 loads, 10 SLICEs
      Net secured_signal_27856: 10 loads, 10 SLICEs
      Net secured_signal_28575: 1 loads, 1 SLICEs
      Net secured_signal_29149: 9 loads, 9 SLICEs
      Net secured_signal_29150: 9 loads, 9 SLICEs
      Net secured_signal_29151: 9 loads, 9 SLICEs
      Net secured_signal_29152: 9 loads, 9 SLICEs
      Net secured_signal_29533: 63 loads, 62 SLICEs
      Net secured_signal_29675: 36 loads, 36 SLICEs
      Net secured_signal_29678: 1 loads, 1 SLICEs
      Net secured_signal_29828: 16 loads, 16 SLICEs
      Net secured_signal_29994: 2 loads, 2 SLICEs
      Net secured_signal_29996: 432 loads, 432 SLICEs
      Net secured_signal_30464: 2 loads, 2 SLICEs
      Net secured_signal_30484: 1 loads, 1 SLICEs
      Net secured_signal_31245: 10 loads, 10 SLICEs
      Net secured_signal_31247: 10 loads, 10 SLICEs
      Net secured_signal_31370: 1 loads, 1 SLICEs
      Net secured_signal_33135: 8 loads, 8 SLICEs
      Net secured_signal_33978: 1 loads, 1 SLICEs
      Net secured_signal_33980: 1 loads, 1 SLICEs
      Net secured_signal_34389: 1 loads, 1 SLICEs
      Net secured_signal_36591: 7 loads, 7 SLICEs
      Net secured_signal_36929: 1 loads, 1 SLICEs
      Net secured_signal_36930: 1 loads, 1 SLICEs
      Net secured_signal_36931: 1 loads, 1 SLICEs
      Net secured_signal_36932: 1 loads, 1 SLICEs
      Net secured_signal_40310: 379 loads, 379 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.arst_n: 1172 loads, 1172 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.srst_n: 4723 loads, 4689 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.phy_srst_n: 1006 loads, 1005 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.sync_rst_n: 28 loads, 27 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.u_int_fifo.u_fifo
     .wr_fifo_en_w: 2 loads, 2 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.u_rsp_fifo.u_fifo
     .wr_fifo_en_w: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo
     .u_fifo_dc.wr_fifo_en_w: 10 loads, 10 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo
     .u_fifo_dc.wr_fifo_en_w: 73 loads, 73 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.ASYNC.u_ctrl_fifo
     .u_fifo_dc.wr_fifo_en_w: 11 loads, 11 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.dp
     ram_wr_d_2: 6 loads, 6 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_ctrl_wrap.s_cpu_rst_n_o: 2 loads, 2
     SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.p_cpu_rst_n_r2: 142 loads, 110 SLICEs
      Net secured_signal_48759: 32 loads, 32 SLICEs
      Net secured_signal_59028: 8 loads, 8 SLICEs
      Net secured_signal_59029: 8 loads, 8 SLICEs
      Net secured_signal_59030: 8 loads, 8 SLICEs
      Net secured_signal_59031: 8 loads, 8 SLICEs
      Net secured_signal_59368: 7 loads, 7 SLICEs
      Net secured_signal_59376: 1 loads, 1 SLICEs
      Net secured_signal_60657: 32 loads, 32 SLICEs
      Net secured_signal_61179: 32 loads, 32 SLICEs
      Net secured_signal_61515: 1 loads, 1 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.wrlvl_load_n_w[0]: 4 loads, 0 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.wr_load_n_w[0]: 4 loads, 0 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.dq_out_adj_load_n_w[0]: 40 loads, 0
     SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.rd_load_n_w[0]: 4 loads, 0 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.dq_in_adj_load_n_w[0]: 32 loads, 0
     SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.cs_adj_load_n_w[0]: 1 loads, 0 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.ca_adj_load_n_w: 6 loads, 0 SLICEs
      Net secured_signal_62061: 8 loads, 8 SLICEs
      Net secured_signal_66379: 8 loads, 8 SLICEs
      Net secured_signal_66380: 8 loads, 8 SLICEs
      Net secured_signal_66381: 8 loads, 8 SLICEs
      Net secured_signal_66382: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.rst_w: 90 loads, 0 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u1_mem_sync.syn
     c_reset: 10 loads, 10 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.dll_rst_w: 1
     loads, 0 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.CA_GRP_ENA.u_ca_grp.un1_cke_l
     ast_r8: 8 loads, 8 SLICEs
      Net lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.CA_GRP_ENA.u_ca_grp.ck_adj_lo
     ad_n_r: 2 loads, 0 SLICEs
      Net pll0_inst.lscc_pll_inst.rstn_i_c_i: 1 loads, 0 SLICEs
   Top 10 highest fanout non-clock nets:
      Net cpu_inst_system_resetn_o_net: 7769 loads
      Net lpddr4_inst.lscc_lpddr4_mc_inst.srst_n: 4724 loads
      Net lpddr4_inst.lscc_lpddr4_mc_inst.arst_n: 1172 loads
      Net secured_signal_15202: 1162 loads
      Net secured_signal_15199: 1162 loads
      Net secured_signal_15198: 1162 loads
      Net secured_signal_15194: 1162 loads
      Net secured_signal_20373: 1041 loads
      Net secured_signal_20369: 1041 loads
      Net secured_signal_20368: 1041 loads

   Number of warnings:  89
   Number of criticals: 3
   Number of errors:    0

Design Errors/Criticals/Warnings

WARNING <1014412> - map: The attribute 'IO_TYPE' of port 'ddr_pll_refclk_i' is
     set to different value in 'ldc_set_port' constraints.
WARNING <71003020> - map: Top module port 'TCK' does not connect to anything.
WARNING <71003020> - map: Top module port 'TMS' does not connect to anything.
WARNING <71003020> - map: Top module port 'TDI' does not connect to anything.
WARNING <71003020> - map: Top module port 'TDO' does not connect to anything.
CRITICAL <52281053> - map:  There is no set_clock_uncertainty constraint on the
     PLL clock output 'CLKOP' of instance 'lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4
     mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst'. Please see FPGA-AN-02059-1.0 -
     Lattice Radiant Timing Constraints Methodology for further details.
CRITICAL <52281053> - map:  There is no set_clock_uncertainty constraint on the
     PLL clock output 'CLKOS' of instance 'lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4
     mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst'. Please see FPGA-AN-02059-1.0 -
     Lattice Radiant Timing Constraints Methodology for further details.
CRITICAL <52281053> - map:  There is no set_clock_uncertainty constraint on the
     PLL clock output 'CLKOP' of instance
     'pll0_inst/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst'. Please see
     FPGA-AN-02059-1.0 - Lattice Radiant Timing Constraints Methodology for
     further details.
WARNING <51011063> - map: IO instance cpu_inst/riscvrtos_inst/secured_instance_1
     87_1/secured_instance_164_1/secured_instance_159_17/secured_instance_511_10
     3 is not connected to any port, it is ignored.
WARNING <51011063> - map: IO instance cpu_inst/riscvrtos_inst/secured_instance_1
     87_1/secured_instance_164_1/secured_instance_159_17/secured_instance_511_10
     4 is not connected to any port, it is ignored.
WARNING <51011063> - map: IO instance cpu_inst/riscvrtos_inst/secured_instance_1
     87_1/secured_instance_164_1/secured_instance_159_17/secured_instance_511_10
     5 is not connected to any port, it is ignored.
WARNING <51011063> - map: IO instance cpu_inst/riscvrtos_inst/secured_instance_1
     87_1/secured_instance_164_1/secured_instance_159_17/secured_instance_511_10
     6 is not connected to any port, it is ignored.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQS[1].u_DQS_BB is
     controlled by IVREF, property BANK_VREF is changed to 'OFF' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQS[2].u_DQS_BB is
     controlled by IVREF, property BANK_VREF is changed to 'OFF' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQS[3].u_DQS_BB is
     controlled by IVREF, property BANK_VREF is changed to 'OFF' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQS[0].u_DQS_BB is
     controlled by IVREF, property BANK_VREF is changed to 'OFF' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[16].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[4].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[25].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[27].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[28].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[5].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[22].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[26].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[30].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[15].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[23].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[24].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[29].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[18].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[21].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[10].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[13].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[2].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[19].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[8].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[11].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[0].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[31].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[17].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[6].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[12].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[1].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[9].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[20].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[7].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[14].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[3].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DMI[3].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DMI[1].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DMI[2].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331043> - map: Port
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DMI[0].u_DQ_BB is
     controlled by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[2].TS_X4.u_TSHX4DQ$r0' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[16].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r1' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[4].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[3].TS_X4.u_TSHX4DQ$r2' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[25].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[3].TS_X4.u_TSHX4DQ$r3' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[27].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[3].TS_X4.u_TSHX4DQ$r4' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[28].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r5' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[5].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[2].TS_X4.u_TSHX4DQ$r6' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[22].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[3].TS_X4.u_TSHX4DQ$r7' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[26].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[3].TS_X4.u_TSHX4DQ$r8' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[30].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r9' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[15].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[2].TS_X4.u_TSHX4DQ$r10' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[23].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[3].TS_X4.u_TSHX4DQ$r11' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[24].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[3].TS_X4.u_TSHX4DQ$r12' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[29].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[2].TS_X4.u_TSHX4DQ$r13' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[18].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[2].TS_X4.u_TSHX4DQ$r14' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[21].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r15' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[10].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r16' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[13].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r17' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[2].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[2].TS_X4.u_TSHX4DQ$r18' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[19].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r19' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[8].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r20' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[11].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r21' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[0].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[3].TS_X4.u_TSHX4DQ$r22' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[31].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[2].TS_X4.u_TSHX4DQ$r23' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[17].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r24' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[6].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r25' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[12].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r26' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[1].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r27' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[9].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[2].TS_X4.u_TSHX4DQ$r28' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[20].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r29' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[7].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r30' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[14].u_DQ_BB.
WARNING <52331031> - map: Tristate DDR 'lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem
     .u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r31' is replicated for
     lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[3].u_DQ_BB.
WARNING <71003020> - map: Top module port 'TCK' does not connect to anything.
WARNING <71003020> - map: Top module port 'TMS' does not connect to anything.
WARNING <71003020> - map: Top module port 'TDI' does not connect to anything.
WARNING <71003020> - map: Top module port 'TDO' does not connect to anything.
WARNING <71003020> - map: Top module port 'TCK' does not connect to anything.
WARNING <71003020> - map: Top module port 'TMS' does not connect to anything.
WARNING <71003020> - map: Top module port 'TDI' does not connect to anything.
WARNING <71003020> - map: Top module port 'TDO' does not connect to anything.

IO (PIO) Attributes

+---------------------+-----------+-----------+-------+-------+-----------+
| IO Name             | Direction | Levelmode |  IO   |  IO   | Special   |
|                     |           |  IO_TYPE  |  REG  |  DDR  | IO Buffer |
+---------------------+-----------+-----------+-------+-------+-----------+
| gpio_io[0]          | BIDIR     | LVCMOS33  | I     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| gpio_io[3]          | BIDIR     | LVCMOS33  | I     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| gpio_io[2]          | BIDIR     | LVCMOS33  | I     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| gpio_io[1]          | BIDIR     | LVCMOS33  | I     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| gpio_io[4]          | BIDIR     | LVCMOS33  | I     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| gpio_io[7]          | BIDIR     | LVCMOS33  | I     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| gpio_io[6]          | BIDIR     | LVCMOS33  | I     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| gpio_io[5]          | BIDIR     | LVCMOS33  | I     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dqs_io[1]       | BIDIR     | LVSTLD_I  |       | O/T   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dqs_io[2]       | BIDIR     | LVSTLD_I  |       | O/T   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dqs_io[3]       | BIDIR     | LVSTLD_I  |       | O/T   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dqs_io[0]       | BIDIR     | LVSTLD_I  |       | O/T   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[16]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[4]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[25]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[27]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[28]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[5]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[22]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[26]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[30]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[15]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[23]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[24]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[29]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[18]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[21]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[10]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[13]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[2]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[19]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[8]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[11]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[0]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[31]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[17]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[6]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[12]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[1]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[9]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[20]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[7]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[14]       | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dq_io[3]        | BIDIR     | LVSTL_I   |       | I/O   |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dmi_io[3]       | BIDIR     | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dmi_io[1]       | BIDIR     | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dmi_io[2]       | BIDIR     | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_dmi_io[0]       | BIDIR     | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_ck_o[0]         | OUTPUT    | LVSTLD_I  |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_cke_o[0]        | OUTPUT    | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_cs_o[0]         | OUTPUT    | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_ca_o[2]         | OUTPUT    | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_ca_o[4]         | OUTPUT    | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_ca_o[0]         | OUTPUT    | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_ca_o[3]         | OUTPUT    | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_ca_o[5]         | OUTPUT    | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_ca_o[1]         | OUTPUT    | LVSTL_I   |       | O     |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| wpj_o               | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| uart_txd_o          | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| uart_rxd_i          | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ss_n_o              | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| sclk_o              | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| rstn_i              | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| mosi_o              | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| miso_i              | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_reset_n_o       | OUTPUT    | LVSTL_I   | O     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| ddr_pll_refclk_i    | INPUT     | LVDS      |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+

Removed logic

Block GSR_INST undriven or does not drive anything - clipped.
Block VCC_cZ was optimized away.
Block lpddr4_inst/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller_s_cpu_rst_n_o_RNI
     H1DE was optimized away.
Block lpddr4_inst/lscc_lpddr4_mc_inst/sync_rst_n_RNIV7HS2 was optimized away.
Block lpddr4_inst/lscc_lpddr4_mc_inst/phy_srst_n_RNI6URQ5 was optimized away.
Block lpddr4_inst/lscc_lpddr4_mc_inst/srst_n_RNIM3AJ3 was optimized away.
Block lpddr4_inst/lscc_lpddr4_mc_inst/arst_n_RNI49JP3 was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk2.lscc_apb2lmmi_0/genblk1.bus_sm_cs_RNI99B
     P4[1] was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk1.lscc_gpio_lmmi_0/genblk2[7].genblk1.genb
     lk1.u_BB_data_RNO was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk1.lscc_gpio_lmmi_0/genblk2[6].genblk1.genb
     lk1.u_BB_data_RNO was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk1.lscc_gpio_lmmi_0/genblk2[5].genblk1.genb
     lk1.u_BB_data_RNO was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk1.lscc_gpio_lmmi_0/genblk2[4].genblk1.genb
     lk1.u_BB_data_RNO was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk1.lscc_gpio_lmmi_0/genblk2[3].genblk1.genb
     lk1.u_BB_data_RNO was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk1.lscc_gpio_lmmi_0/genblk2[2].genblk1.genb
     lk1.u_BB_data_RNO was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk1.lscc_gpio_lmmi_0/genblk2[1].genblk1.genb
     lk1.u_BB_data_RNO was optimized away.
Block gpio0_inst/lscc_gpio_inst/genblk1.lscc_gpio_lmmi_0/genblk2[0].genblk1.genb
     lk1.u_BB_data_RNO was optimized away.

PLL/DLL Summary

PLL 1:                                 Pin/Node Value
  PLL Instance Name:                            lpddr4_inst/lscc_lpddr4_mc_inst/
       u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst
  Input Reference Clock:               PIN      ddr_pll_refclk_i_c
  Output Clock(P):                     NODE
       lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.clkop_o
  Output Clock(S):                     NODE
       lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w
  Output Clock(S2):                             NONE
  Output Clock(S3):                             NONE
  Output Clock(S4):                             NONE
  Output Clock(S5):                             NONE
  Feedback Signal:                     NODE
       lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.clkop_o
  Reset Signal:                        NODE     cpu_inst_system_resetn_o_net_i
  Standby Signal:                      NODE     GND
  PLL LOCK signal:                     NODE
       lpddr4_inst.lscc_lpddr4_mc_inst.u_lp4mem.pll_lock_o
  PLL Internal LOCK Signal:                     NONE
  A Divider:                                    7
  B Divider:                                    1
  C Divider:                                    7
  D Divider:                                    7
  E Divider:                                    7
  F Divider:                                    7
  A Post Divider Shift:                         7
  B Post Divider Shift:                         1
  C Post Divider Shift:                         7
  D Post Divider Shift:                         7
  E Post Divider Shift:                         7
  F Post Divider Shift:                         7
  A Section VCO Phase Shift:                    0
  B Section VCO Phase Shift:                    0
  C Section VCO Phase Shift:                    0
  D Section VCO Phase Shift:                    0
  E Section VCO Phase Shift:                    0
  F Section VCO Phase Shift:                    0
  CLKOP Trim Setting:                           0000
  CLKOS Trim Setting:                           0000
  CLKOS2 Trim Setting:                          0000
  CLKOS3 Trim Setting:                          0000
  CLKOS4 Trim Setting:                          0000
  CLKOS5 Trim Setting:                          0000
PLL 2:                                 Pin/Node Value
  PLL Instance Name:                            pll0_inst/lscc_pll_inst/gen_no_r
       efclk_mon.u_PLL.PLL_inst
  Input Reference Clock:               NODE     osc0_inst_hf_clk_out_o_net
  Output Clock(P):                     NODE     pll0_inst_clkop_o_net
  Output Clock(S):                              NONE
  Output Clock(S2):                             NONE
  Output Clock(S3):                             NONE
  Output Clock(S4):                             NONE
  Output Clock(S5):                             NONE
  Feedback Signal:                     NODE
       pll0_inst.lscc_pll_inst.intclkop_w
  Reset Signal:                        NODE
       pll0_inst.lscc_pll_inst.rstn_i_c_i
  Standby Signal:                      NODE     GND
  PLL LOCK signal:                     NODE     pll0_inst_lock_o_net
  PLL Internal LOCK Signal:                     NONE
  A Divider:                                    31
  B Divider:                                    7
  C Divider:                                    7
  D Divider:                                    7
  E Divider:                                    7
  F Divider:                                    7
  A Post Divider Shift:                         31
  B Post Divider Shift:                         7
  C Post Divider Shift:                         7
  D Post Divider Shift:                         7
  E Post Divider Shift:                         7
  F Post Divider Shift:                         7
  A Section VCO Phase Shift:                    0
  B Section VCO Phase Shift:                    0
  C Section VCO Phase Shift:                    0
  D Section VCO Phase Shift:                    0
  E Section VCO Phase Shift:                    0
  F Section VCO Phase Shift:                    0
  CLKOP Trim Setting:                           0000
  CLKOS Trim Setting:                           0000
  CLKOS2 Trim Setting:                          0000
  CLKOS3 Trim Setting:                          0000
  CLKOS4 Trim Setting:                          0000
  CLKOS5 Trim Setting:                          0000

OSC Summary

OSC 1:                                 Pin/Node Value
  OSC Instance Name:                            osc0_inst/lscc_osc_inst/gen_osca
       .u_OSC_A.OSCA_inst
  Enable High Frequency SDSC:          NODE     VCC
  High Frequency Output:               NODE     osc0_inst_hf_clk_out_o_net
  Low Frequency Output:                NODE     osc0_inst_lf_clk_out_o_net
  SDC Output:                                   NONE
  High Frequency DIV:                           8

ASIC Components

Instance Name: secured_comp_18314
         Type: DCC
Instance Name: secured_comp_18355
         Type: CONFIG_JTAG_CORE
Instance Name: secured_comp_22634
         Type: EBR_CORE
Instance Name: secured_comp_22635
         Type: EBR_CORE
Instance Name: secured_comp_22636
         Type: EBR_CORE
Instance Name: secured_comp_22637
         Type: EBR_CORE
Instance Name: secured_comp_23623
         Type: EBR_CORE
Instance Name: secured_comp_23624
         Type: EBR_CORE
Instance Name: secured_comp_23625
         Type: EBR_CORE
Instance Name: secured_comp_23626
         Type: EBR_CORE
Instance Name: secured_comp_23627
         Type: EBR_CORE
Instance Name: secured_comp_23628
         Type: EBR_CORE
Instance Name: secured_comp_23629
         Type: EBR_CORE
Instance Name: secured_comp_23630
         Type: EBR_CORE
Instance Name: secured_comp_23631
         Type: EBR_CORE
Instance Name: secured_comp_23632
         Type: EBR_CORE
Instance Name: secured_comp_26580
         Type: PREADD9_CORE
Instance Name: secured_comp_26581
         Type: PREADD9_CORE
Instance Name: secured_comp_26582
         Type: MULT9_CORE
Instance Name: secured_comp_26583
         Type: MULT9_CORE
Instance Name: secured_comp_26584
         Type: MULT18_CORE
Instance Name: secured_comp_26585
         Type: REG18_CORE
Instance Name: secured_comp_26586
         Type: REG18_CORE
Instance Name: secured_comp_26587
         Type: PREADD9_CORE
Instance Name: secured_comp_26588
         Type: PREADD9_CORE
Instance Name: secured_comp_26589
         Type: PREADD9_CORE
Instance Name: secured_comp_26590
         Type: PREADD9_CORE
Instance Name: secured_comp_26591
         Type: MULT9_CORE
Instance Name: secured_comp_26592
         Type: MULT9_CORE
Instance Name: secured_comp_26593
         Type: MULT9_CORE
Instance Name: secured_comp_26594
         Type: MULT9_CORE
Instance Name: secured_comp_26595
         Type: MULT18_CORE
Instance Name: secured_comp_26596
         Type: MULT18_CORE
Instance Name: secured_comp_26597
         Type: MULT18X36_CORE
Instance Name: secured_comp_26598
         Type: REG18_CORE
Instance Name: secured_comp_26599
         Type: REG18_CORE
Instance Name: secured_comp_26600
         Type: REG18_CORE
Instance Name: secured_comp_26601
         Type: PREADD9_CORE
Instance Name: secured_comp_26602
         Type: PREADD9_CORE
Instance Name: secured_comp_26603
         Type: PREADD9_CORE
Instance Name: secured_comp_26604
         Type: PREADD9_CORE
Instance Name: secured_comp_26605
         Type: MULT9_CORE
Instance Name: secured_comp_26606
         Type: MULT9_CORE
Instance Name: secured_comp_26607
         Type: MULT9_CORE
Instance Name: secured_comp_26608
         Type: MULT9_CORE
Instance Name: secured_comp_26609
         Type: MULT18_CORE
Instance Name: secured_comp_26610
         Type: MULT18_CORE
Instance Name: secured_comp_26611
         Type: MULT18X36_CORE
Instance Name: secured_comp_26612
         Type: REG18_CORE
Instance Name: secured_comp_26613
         Type: REG18_CORE
Instance Name: secured_comp_26614
         Type: REG18_CORE
Instance Name: secured_comp_26615
         Type: PREADD9_CORE
Instance Name: secured_comp_26616
         Type: PREADD9_CORE
Instance Name: secured_comp_26617
         Type: MULT9_CORE
Instance Name: secured_comp_26618
         Type: MULT9_CORE
Instance Name: secured_comp_26619
         Type: MULT18_CORE
Instance Name: secured_comp_26620
         Type: REG18_CORE
Instance Name: secured_comp_26621
         Type: REG18_CORE
Instance Name: secured_comp_26622
         Type: EBR_CORE
Instance Name: secured_comp_26623
         Type: EBR_CORE
Instance Name: secured_comp_26624
         Type: EBR_CORE
Instance Name: secured_comp_26625
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_bu
     ff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUT
     E[0].DATA_ROUTE[0].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_bu
     ff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUT
     E[0].DATA_ROUTE[2].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_bu
     ff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUT
     E[0].DATA_ROUTE[5].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_bu
     ff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUT
     E[0].DATA_ROUTE[1].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_bu
     ff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUT
     E[0].DATA_ROUTE[4].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_bu
     ff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUT
     E[0].DATA_ROUTE[7].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_bu
     ff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUT
     E[0].DATA_ROUTE[3].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_bu
     ff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUT
     E[0].DATA_ROUTE[6].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
         Type: EBR_CORE
Instance Name: secured_comp_32562
         Type: EBR_CORE
Instance Name: secured_comp_32563
         Type: EBR_CORE
Instance Name: secured_comp_32564
         Type: EBR_CORE
Instance Name: secured_comp_32565
         Type: EBR_CORE
Instance Name: secured_comp_32566
         Type: EBR_CORE
Instance Name: secured_comp_32567
         Type: EBR_CORE
Instance Name: secured_comp_32568
         Type: EBR_CORE
Instance Name: secured_comp_32569
         Type: EBR_CORE
Instance Name: secured_comp_32570
         Type: EBR_CORE
Instance Name: secured_comp_44722
         Type: EBR_CORE
Instance Name: secured_comp_44723
         Type: EBR_CORE
Instance Name: secured_comp_44724
         Type: EBR_CORE
Instance Name: secured_comp_44725
         Type: EBR_CORE
Instance Name: secured_comp_44726
         Type: EBR_CORE
Instance Name: secured_comp_44727
         Type: EBR_CORE
Instance Name: secured_comp_44728
         Type: EBR_CORE
Instance Name: secured_comp_44730
         Type: EBR_CORE
Instance Name: secured_comp_44731
         Type: EBR_CORE
Instance Name: secured_comp_44733
         Type: EBR_CORE
Instance Name: secured_comp_44735
         Type: EBR_CORE
Instance Name: secured_comp_44736
         Type: EBR_CORE
Instance Name: secured_comp_44737
         Type: EBR_CORE
Instance Name: secured_comp_44740
         Type: EBR_CORE
Instance Name: secured_comp_44741
         Type: EBR_CORE
Instance Name: secured_comp_44742
         Type: EBR_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_DDRDLL.
     DDRDLL_inst
         Type: DDRDLL_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYN
     C.ECLKSYNC_inst
         Type: ECLKSYNC_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV
     .ECLKDIV_inst
         Type: ECLKDIV_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[3].VR
     EF.u0_DQSBUF.DQSBUFA_inst
         Type: DQSBUFA_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[3].VR
     EF.u0_DQSBUF.BNKVRGEN18_inst
         Type: IVREF_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[1].VR
     EF.u0_DQSBUF.DQSBUFA_inst
         Type: DQSBUFA_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[1].VR
     EF.u0_DQSBUF.BNKVRGEN18_inst
         Type: IVREF_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[2].VR
     EF.u0_DQSBUF.DQSBUFA_inst
         Type: DQSBUFA_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[2].VR
     EF.u0_DQSBUF.BNKVRGEN18_inst
         Type: IVREF_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[0].VR
     EF.u0_DQSBUF.DQSBUFA_inst
         Type: DQSBUFA_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[0].VR
     EF.u0_DQSBUF.BNKVRGEN18_inst
         Type: IVREF_CORE
Instance Name: lpddr4_inst/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.
     u_PLL.PLL_inst
         Type: PLL_CORE
Instance Name: osc0_inst/lscc_osc_inst/gen_osca.u_OSC_A.OSCA_inst
         Type: OSC_CORE
Instance Name: pll0_inst/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst
         Type: PLL_CORE
Instance Name: secured_comp_50804
         Type: EBR_CORE
Instance Name: system0_inst/lscc_sys_mem_inst/CORE_MEMORY.genblk1.u_lscc_mem0/in
     tf_AXI4.lram.ulram_0/genblk2[0].genblk3.ulram_core0/u_lram0.LRAM_inst
         Type: LRAM_CORE
Instance Name: system0_inst/lscc_sys_mem_inst/CORE_MEMORY.genblk1.u_lscc_mem0/in
     tf_AXI4.lram.ulram_0/genblk2[1].genblk3.ulram_core0/u_lram0.LRAM_inst
         Type: LRAM_CORE

Constraint Summary

   Total number of constraints: 272
   Total number of constraints dropped: 0

Run Time and Memory Usage

   Total CPU Time: 48 secs
   Total REAL Time: 50 secs
   Peak Memory Usage: 1765 MB
Checksum -- map: fcc4f075113eb2bd821f11d03dac15d67adf8320
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Copyright (c) 1995
     AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent
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Copyright (c) 2001 Agere Systems
     All rights reserved.
Copyright (c) 2002-2024 Lattice Semiconductor
     Corporation,  All rights reserved.
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