BITGEN: Bitstream Generator Radiant Software (64-bit) 2024.1.1.259.1 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2024 Lattice Semiconductor Corporation, All rights reserved. Fri Oct 18 11:51:03 2024 Command: bitgen -w -gui -msgset C:/LAB3/WS/cpnx_riscv_rx_rd/promote.xml -g REGISTER_INIT:ON cpnx_riscv_rx_rd_impl_1.udb C:/LAB3/WS/cpnx_riscv_rx_rd/impl_1/cpnx_riscv_rx_rd_impl_1 Running DRC. WARNING <71003020> - Top module port 'TCK' does not connect to anything. WARNING <71003020> - Top module port 'TMS' does not connect to anything. WARNING <71003020> - Top module port 'TDI' does not connect to anything. WARNING <71003020> - Top module port 'TDO' does not connect to anything. DRC detected 0 errors and 0 warnings. Preference Summary: +---------------------------------+---------------------------------+ | Preference | Current Setting | +---------------------------------+---------------------------------+ | DONE_EX | OFF* | +---------------------------------+---------------------------------+ | DONE_OD | ON* | +---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF* | +---------------------------------+---------------------------------+ | EARLY_IO_RELEASE | OFF* | +---------------------------------+---------------------------------+ | REGISTER_INIT | ON** | +---------------------------------+---------------------------------+ | MASTER_PREAMBLE_TIMER_CYCLES | 600000* | +---------------------------------+---------------------------------+ | SLAVE_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | SLAVE_I2C_PORT | DISABLE** | +---------------------------------+---------------------------------+ | SLAVE_I3C_PORT | DISABLE** | +---------------------------------+---------------------------------+ | JTAG_PORT | ENABLE** | +---------------------------------+---------------------------------+ | DONE_PORT | ENABLE** | +---------------------------------+---------------------------------+ | INITN_PORT | ENABLE** | +---------------------------------+---------------------------------+ | PROGRAMN_PORT | ENABLE** | +---------------------------------+---------------------------------+ | TRANSFR | ON | +---------------------------------+---------------------------------+ | MASTER_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MCCLK_FREQ | 112.5 | +---------------------------------+---------------------------------+ | COMPRESS_CONFIG | OFF* | +---------------------------------+---------------------------------+ | BACKGROUND_RECONFIG | OFF* | +---------------------------------+---------------------------------+ | CONFIG_IOSLEW | FAST | +---------------------------------+---------------------------------+ | WAKE_UP | ENABLE_DONE_SYNC** | +---------------------------------+---------------------------------+ | BOOTMODE | SINGLE | +---------------------------------+---------------------------------+ | CONFIGIO_VOLTAGE_BANK0 | NOT_SPECIFIED* | +---------------------------------+---------------------------------+ | CONFIGIO_VOLTAGE_BANK1 | 3.3 | +---------------------------------+---------------------------------+ * Default setting. ** The specified setting matches the default setting. Creating bit map... Bitstream Status: Final Version 4.5. Saving bit stream in "C:/LAB3/WS/cpnx_riscv_rx_rd/impl_1/cpnx_riscv_rx_rd_impl_1.bit". Bitstream generation complete! Note: Found debugger inserted in the design