| cpnx_riscv_rx_rd | 1876(1) | 2999(0) | 67(10) | 8(0) | 103(0) | 219(0) | 2(0) |
| apb_interconnect0_inst | 65(0) | 4(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| lscc_apb_interconnect_inst | 65(0) | 4(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| apb_bus.u_lscc_apb_bus | 65(0) | 4(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_lscc_apb_decoder | 12(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[0].u_lscc_apb_decoder_sel | 4(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[0].u_lscc_apb_decoder_comp | 4(4) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[1].u_lscc_apb_decoder_sel | 3(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[0].u_lscc_apb_decoder_comp | 3(3) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[2].u_lscc_apb_decoder_sel | 5(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[0].u_lscc_apb_decoder_comp | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_lscc_apb_multiplexor | 53(53) | 4(4) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| axi2ahbl_spi_flash_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| axi2apb0_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| axi_interconnect_0_inst | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| cpu_inst | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| gpio0_inst | 109(0) | 97(0) | 8(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| lscc_gpio_inst | 109(0) | 97(0) | 8(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1.lscc_gpio_lmmi_0 | 97(97) | 72(72) | 8(8) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk2.lscc_apb2lmmi_0 | 12(12) | 25(25) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| lpddr4_inst | 1177(0) | 2551(0) | 49(0) | 8(0) | 103(0) | 174(0) | 0(0) |
| lscc_lpddr4_mc_inst | 1177(4) | 2551(99) | 49(0) | 8(0) | 103(0) | 174(0) | 0(0) |
| AXI_BI.u_axi_if | 968(0) | 2146(0) | 0(0) | 8(0) | 103(0) | 165(0) | 0(0) |
| u_rd | 360(59) | 1030(93) | 0(0) | 8(0) | 17(0) | 153(0) | 0(0) |
| ASYNC.u_ctrl_fifo | 23(0) | 67(0) | 0(0) | 0(0) | 11(0) | 0(0) | 0(0) |
| u_fifo_dc | 23(23) | 67(67) | 0(0) | 0(0) | 11(11) | 0(0) | 0(0) |
| u_reorder_buff | 278(270) | 870(814) | 0(0) | 8(0) | 6(0) | 153(153) | 0(0) |
| EBR_CTRL[0].ASYNC.u_enable_bus_sync | 1(1) | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[0].ASYNC.u_not_empty_sync | 0(0) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[1].ASYNC.u_enable_bus_sync | 1(1) | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[1].ASYNC.u_not_empty_sync | 0(0) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[2].ASYNC.u_enable_bus_sync | 1(1) | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[2].ASYNC.u_not_empty_sync | 0(0) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[3].ASYNC.u_enable_bus_sync | 1(1) | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[3].ASYNC.u_not_empty_sync | 0(0) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[4].ASYNC.u_enable_bus_sync | 1(1) | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[4].ASYNC.u_not_empty_sync | 0(0) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[5].ASYNC.u_enable_bus_sync | 1(1) | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[5].ASYNC.u_not_empty_sync | 0(0) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[6].ASYNC.u_enable_bus_sync | 1(1) | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[6].ASYNC.u_not_empty_sync | 0(0) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[7].ASYNC.u_enable_bus_sync | 1(1) | 5(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| EBR_CTRL[7].ASYNC.u_not_empty_sync | 0(0) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_ctrl_dpram | 0(0) | 0(0) | 0(0) | 0(0) | 6(0) | 0(0) | 0(0) |
| lscc_distributed_dpram_inst | 0(0) | 0(0) | 0(0) | 0(0) | 6(6) | 0(0) | 0(0) |
| u_lpddr4_mc_rd_rtrn_ebr_inst | 0(0) | 0(0) | 0(0) | 8(0) | 0(0) | 0(0) | 0(0) |
| lscc_ram_dp_inst | 0(0) | 0(0) | 0(0) | 8(0) | 0(0) | 0(0) | 0(0) |
| mem_main | 0(0) | 0(0) | 0(0) | 8(0) | 0(0) | 0(0) | 0(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[0].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[1].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[2].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[3].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[4].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[5].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[6].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[7].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) |
| u_wr | 608(410) | 1116(633) | 0(0) | 0(0) | 86(0) | 12(5) | 0(0) |
| ASYNC.u_ctrl_fifo | 29(0) | 63(0) | 0(0) | 0(0) | 10(0) | 0(0) | 0(0) |
| u_fifo_dc | 29(29) | 63(63) | 0(0) | 0(0) | 10(10) | 0(0) | 0(0) |
| ASYNC.u_data_fifo | 43(0) | 330(0) | 0(0) | 0(0) | 73(0) | 7(0) | 0(0) |
| u_fifo_dc | 43(43) | 330(330) | 0(0) | 0(0) | 73(73) | 7(7) | 0(0) |
| u_int_fifo | 25(0) | 48(0) | 0(0) | 0(0) | 2(0) | 0(0) | 0(0) |
| u_fifo | 25(25) | 48(48) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| u_rsp_fifo | 101(0) | 42(0) | 0(0) | 0(0) | 1(0) | 0(0) | 0(0) |
| u_fifo | 101(101) | 42(42) | 0(0) | 0(0) | 1(1) | 0(0) | 0(0) |
| i_apb_cdc | 72(72) | 232(232) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_ctrl_wrap | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_lp4mem | 132(48) | 74(9) | 49(0) | 0(0) | 0(0) | 9(4) | 0(0) |
| CA_GRP_ENA.u_ca_grp | 17(17) | 24(24) | 9(9) | 0(0) | 0(0) | 5(5) | 0(0) |
| u1_clock_sync | 63(0) | 41(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u1_mem_sync | 63(63) | 41(41) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_dq_dqs_dm | 0(0) | 0(0) | 40(40) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_pll | 4(4) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| osc0_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| lscc_osc_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| pll0_inst | 1(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| lscc_pll_inst | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| spi_flash1_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| system0_inst | 520(0) | 347(0) | 0(0) | 0(0) | 0(0) | 45(0) | 2(0) |
| lscc_sys_mem_inst | 520(0) | 347(0) | 0(0) | 0(0) | 0(0) | 45(0) | 2(0) |
| AXI4_ARB.u_arbiter | 0(0) | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| CORE_MEMORY.genblk1.u_lscc_mem0 | 2(0) | 2(0) | 0(0) | 0(0) | 0(0) | 0(0) | 2(0) |
| intf_AXI4.lram.ulram_0 | 2(2) | 2(2) | 0(0) | 0(0) | 0(0) | 0(0) | 2(0) |
| genblk2[0].genblk3.ulram_core0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| genblk2[1].genblk3.ulram_core0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| bridge_s0.genblk1.bridge_s0 | 518(518) | 344(344) | 0(0) | 0(0) | 0(0) | 45(45) | 0(0) |