#--  Synopsys, Inc.
#--  Version V-2023.09LR-1
#--  Project file C:\LAB3\WS\cpnx_riscv_rx_rd\impl_1\run_options.txt
#--  Written on Fri Oct 18 10:32:18 2024


#project files
add_file -constraint "C:/lscc/radiant/2024.1/scripts/tcl/flow/radiant_synplify_vars.tcl"
add_file -constraint "cpnx_riscv_rx_rd_impl_1_cpe.ldc"
add_file -verilog "C:/lscc/radiant/2024.1/ip/pmi/pmi_lfcpnx.v"
add_file -vhdl -lib pmi "C:/lscc/radiant/2024.1/ip/pmi/pmi_lfcpnx.vhd"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/system0/2.2.0/rtl/system0.v"
add_file -verilog -vlog_std sysv "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/new_lpddr4/2.1.0/rtl/new_lpddr4.sv"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/spi_flash1/1.9.0/rtl/spi_flash1.v"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd.v"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/axi2ahbl_spi_flash/1.1.0/rtl/axi2ahbl_spi_flash.v"
add_file -verilog -vlog_std sysv "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/axi_interconnect_0/1.2.2/rtl/axi_interconnect_0.sv"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/module/osc0/1.4.0/rtl/osc0.v"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/gpio0/1.6.1/rtl/gpio0.v"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/axi2apb0/1.1.1/rtl/axi2apb0.v"
add_file -verilog -vlog_std sysv "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/cpu/2.4.0/rtl/cpu.sv"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/module/apb_interconnect0/1.2.1/rtl/apb_interconnect0.v"
add_file -verilog -vlog_std v2001 "C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/module/pll0/1.9.0/rtl/pll0.v"


#implementation: "impl_1"
impl -add impl_1 -type fpga

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {C:/LAB3/WS/cpnx_riscv_rx_rd;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/axi2ahbl_spi_flash/1.1.0;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/axi2apb0/1.1.1;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/axi_interconnect_0/1.2.2;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/cpu/2.4.0;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/gpio0/1.6.1;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/new_lpddr4/2.1.0;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/spi_flash1/1.9.0;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/ip/system0/2.2.0;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/module/apb_interconnect0/1.2.1;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/module/osc0/1.4.0;C:/LAB3/WS/cpnx_riscv_rx_rd/cpnx_riscv_rx_rd/lib/latticesemi.com/module/pll0/1.9.0}

#device options
set_option -technology LFCPNX
set_option -part LFCPNX_100
set_option -package BBG484C
set_option -speed_grade -8
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "cpnx_riscv_rx_rd"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -scm2hydra 0
set_option -scm2hydra_preserve_rtl_sig 1
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 200
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_structural_verilog 0
set_option -write_vhdl 0

# Lattice XP
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -infer_seqShift 1
set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 0
set_option -rw_check_on_ram 0
set_option -update_models_cp 0
set_option -syn_edif_array_rename 0
set_option -Write_declared_clocks_only 1
set_option -seqshift_no_replicate 0
set_option -run_design_rule_checker 0
set_option -design_rule_fanout_limit 0
set_option -acp_debug_info 0

# Lattice LFCPNX
set_option -s44_optimization 0
set_option -infer_widefn 1
set_option -pack_rst_largeram 1

# NFilter
set_option -no_sequential_opt 0

# common_options
set_option -add_dut_hierarchy 0
set_option -prepare_readback 0

# flow_options
set_option -slr_aware_debug 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./cpnx_riscv_rx_rd_impl_1.vm"

#set log file 
set_option log_file "C:/LAB3/WS/cpnx_riscv_rx_rd/impl_1/cpnx_riscv_rx_rd_impl_1.srf" 
impl -active "impl_1"
