@W: CG289 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\axi_interconnect_0\1.2.2\rtl\axi_interconnect_0.sv":10000:88:10000:91|Specified digits overflow the number's size
@W: CG289 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\axi_interconnect_0\1.2.2\rtl\axi_interconnect_0.sv":13373:88:13373:91|Specified digits overflow the number's size
@W: CG289 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\axi_interconnect_0\1.2.2\rtl\axi_interconnect_0.sv":10000:88:10000:91|Specified digits overflow the number's size
@W: CG289 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\axi_interconnect_0\1.2.2\rtl\axi_interconnect_0.sv":13373:88:13373:91|Specified digits overflow the number's size
@W: CG360 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\apb_interconnect0\1.2.1\rtl\apb_interconnect0.v":1170:30:1170:50|Removing wire apb_prdata_def_mstr_w, as there is no assignment to it.
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":273:26:273:26|Input req_ready on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":280:27:280:27|Input resp_valid on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":282:28:282:28|Input resp_data_1 on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":283:30:283:30|Input resp_status_1 on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":290:28:290:28|Input resp_data_0 on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":291:30:291:30|Input resp_status_0 on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":315:32:315:32|Input dBusAxi_b_buser on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":335:32:335:32|Input dBusAxi_r_ruser on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":359:32:359:32|Input iBusAxi_b_buser on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":379:32:379:32|Input iBusAxi_r_ruser on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":383:31:383:31|Input ibus_cmd_ready on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":391:31:391:31|Input ibus_rsp_valid on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":392:38:392:38|Input ibus_rsp_payload_last on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":393:38:393:38|Input ibus_rsp_payload_data on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":394:39:394:39|Input ibus_rsp_payload_error on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":396:31:396:31|Input dbus_cmd_ready on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":405:31:405:31|Input dbus_rsp_valid on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":406:38:406:38|Input dbus_rsp_payload_last on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":407:38:407:38|Input dbus_rsp_payload_data on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":408:39:408:39|Input dbus_rsp_payload_error on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":409:43:409:43|Input dbus_rsp_payload_exclusive on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":410:31:410:31|Input dbus_inv_valid on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":412:38:412:38|Input dbus_inv_payload_last on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":413:49:413:49|Input dbus_inv_payload_fragment_enable on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":414:50:414:50|Input dbus_inv_payload_fragment_address on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":416:31:416:31|Input dbus_ack_ready on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":419:20:419:20|Input TDI on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":421:20:421:20|Input TCK on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\cpu\2.4.0\rtl\cpu.sv":422:20:422:20|Input TMS on instance riscvrtos_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\gpio0\1.6.1\rtl\gpio0.v":777:36:777:41|*Output gpio_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\gpio0\1.6.1\rtl\gpio0.v":778:36:778:44|*Output gpio_en_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\gpio0\1.6.1\rtl\gpio0.v":530:36:530:47|*Output lmmi_rdata_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\gpio0\1.6.1\rtl\gpio0.v":531:11:531:28|*Output lmmi_rdata_valid_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\gpio0\1.6.1\rtl\gpio0.v":532:11:532:22|*Output lmmi_ready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":431:30:431:48|Type of parameter DDR_CMD_FREQ on the instance lscc_lpddr4_mc_inst is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":431:30:431:48|Type of parameter CK_DELAY_VAL on the instance lscc_lpddr4_mc_inst is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60771:35:60771:45|Type of parameter DDR_CMD_FREQ on the instance u_ctrl_wrap is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":61070:35:61070:42|Type of parameter CLK_FREQ on the instance u_lp4mem is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":61070:35:61070:42|Type of parameter CK_DELAY_VAL on the instance u_lp4mem is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter CLKOS2_TRIM on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter CLKOS3_TRIM on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter CLKOS4_TRIM on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter CLKOS5_TRIM on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter DELAY_CTRL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter DIRECTION on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter DYN_SEL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter ENABLE_SYNC on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FAST_LOCK_EN on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FBK_CUR_BLE on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FBK_EDGE_SEL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FBK_IF_TIMING_CTL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FBK_MODE on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FBK_PI_BYPASS on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FBK_PI_RC on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FBK_PR_CC on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FBK_PR_IC on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FLOAT_CP on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FLOCK_CTRL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FLOCK_EN on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FLOCK_SRC_SEL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter FORCE_FILTER on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter I_CTRL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter IPI_COMP_EN on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter LDT_INT_LOCK_STICKY on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter LDT_LOCK on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter LOAD_REG on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter OPENLOOP_EN on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter REF_MMD_IN on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter REF_TIMING_CTL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter REFIN_RESET on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter RESET_LF on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter ROTATE on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter SLEEP on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter STDBY_ATT on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter TRIMOS2_BYPASS_N on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter TRIMOS3_BYPASS_N on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter TRIMOS4_BYPASS_N on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter TRIMOS5_BYPASS_N on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter PHASE_SEL_DEL on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter PHASE_SEL_DEL_P1 on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18080:67:18080:71|Type of parameter EXTERNAL_DIVIDE_FACTOR on the instance u_PLL is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":17080:16:17080:24|*Output refdetlos has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":17099:16:17099:27|*Output apb_pready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":17100:16:17100:28|*Output apb_pslverr_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":17101:22:17101:33|*Output apb_prdata_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG168 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":18978:53:18978:60|Type of parameter CK_DELAY_VAL on the instance u_ca_grp is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":745:11:745:23|*Output one_err_det_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":746:11:746:23|*Output two_err_det_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":1154:16:1154:21|Sharing sequential element async_rd_controller.empty_ext_r and merging async_rd_controller.empty_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":1000:24:1000:29|Sharing sequential element afull_flag_impl.async.af_flag_ext_r and merging afull_flag_impl.async.af_flag_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":901:16:901:21|Sharing sequential element async_wr_controller.wr_addr_arith_r and merging async_wr_controller.wr_addr_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":901:16:901:21|Sharing sequential element async_wr_controller.full_ext_r and merging async_wr_controller.full_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":745:11:745:23|*Output one_err_det_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":746:11:746:23|*Output two_err_det_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":1154:16:1154:21|Sharing sequential element async_rd_controller.empty_ext_r and merging async_rd_controller.empty_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":1000:24:1000:29|Sharing sequential element afull_flag_impl.async.af_flag_ext_r and merging afull_flag_impl.async.af_flag_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":901:16:901:21|Sharing sequential element async_wr_controller.wr_addr_arith_r and merging async_wr_controller.wr_addr_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":901:16:901:21|Sharing sequential element async_wr_controller.full_ext_r and merging async_wr_controller.full_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL271 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":20448:4:20448:12|Pruning unused bits 7 to 5 of start_addr_d[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL208 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":20380:4:20380:12|All reachable assignments to bit 2 of wr_strb_fifo_wrdata[34:0] assign 0, register removed by optimization.
@W: CG532 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":1578:4:1578:10|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CL271 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21392:4:21392:9|Pruning unused bits 23 to 22 of dpram_rddata_d[23:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60136:11:60136:24|*Output wr_req_ready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60143:11:60143:20|*Output wr_ready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60148:11:60148:24|*Output rd_req_ready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60156:11:60156:24|*Output rd_rsp_valid_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60157:34:60157:44|*Output rd_rsp_id_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60158:36:60158:52|*Output rd_rsp_order_id_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60159:40:60159:52|*Output rd_rsp_data_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60160:35:60160:46|*Output rd_rsp_len_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60161:23:60161:35|*Output rd_rsp_size_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60162:17:60162:34|*Output rd_rsp_buff_addr_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60173:31:60173:40|*Output ddr_addr_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60174:17:60174:24|*Output ddr_ba_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60175:11:60175:20|*Output ddr_we_n_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60176:11:60176:21|*Output ddr_cas_n_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":60177:11:60177:21|*Output ddr_ras_n_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\osc0\1.4.0\rtl\osc0.v":123:11:123:19|*Output cfg_clk_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\osc0\1.4.0\rtl\osc0.v":124:11:124:21|*Output smclk_rst_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\osc0\1.4.0\rtl\osc0.v":125:11:125:20|*Output sedc_rst_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\osc0\1.4.0\rtl\osc0.v":126:11:126:20|*Output lmmi_clk_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\osc0\1.4.0\rtl\osc0.v":127:11:127:23|*Output lmmi_resetn_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\pll0\1.9.0\rtl\pll0.v":287:16:287:24|*Output refdetlos has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\pll0\1.9.0\rtl\pll0.v":306:16:306:27|*Output apb_pready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\pll0\1.9.0\rtl\pll0.v":307:16:307:28|*Output apb_pslverr_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\pll0\1.9.0\rtl\pll0.v":308:23:308:34|*Output apb_prdata_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL260 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":2820:4:2820:9|Pruning register bit 0 of axi_rresp_r[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":2690:4:2690:9|Pruning register bits 7 to 3 of mem_arsize_r[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":2291:4:2291:9|Pruning register bit 0 of axi_bresp_r[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":6818:38:6818:38|Input dps_i on instance ulram_core0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":6818:38:6818:38|Input dps_i on instance ulram_core0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CL271 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":7007:32:7007:37|Pruning unused bits 13 to 0 of genblk3.genblk3.genblk1.addr_b_p_r[14:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":7007:32:7007:37|Pruning unused bits 13 to 0 of genblk3.genblk3.genblk1.addr_b_p2_r[14:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":6910:32:6910:37|Pruning unused bits 13 to 0 of genblk3.genblk1.genblk1.addr_a_p_r[14:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":6910:32:6910:37|Pruning unused bits 13 to 0 of genblk3.genblk1.genblk1.addr_a_p2_r[14:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":4671:46:4671:46|Input dps_i on instance ulram_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CL207 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":1683:16:1683:21|All reachable assignments to s0_prio.axi_s1_wready_reg assign 0, register removed by optimization.
@W: CL207 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":1683:16:1683:21|All reachable assignments to s0_prio.axi_s1_awready_reg assign 0, register removed by optimization.
@W: CL207 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":1683:16:1683:21|All reachable assignments to s0_prio.axi_s1_arready_reg assign 0, register removed by optimization.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":1683:16:1683:21|Sharing sequential element s0_prio.axi_s0_awready_reg and merging s0_prio.axi_s0_wready_reg. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":1683:16:1683:21|Sharing sequential element s0_prio.axi_s0_arready_reg and merging s0_prio.axi_s0_wready_reg. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8554:16:8554:34|*Output ahbl_s0_hreadyout_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8555:16:8555:30|*Output ahbl_s0_hresp_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8556:37:8556:52|*Output ahbl_s0_hrdata_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8572:16:8572:34|*Output ahbl_s1_hreadyout_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8573:16:8573:30|*Output ahbl_s1_hresp_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8574:37:8574:52|*Output ahbl_s1_hrdata_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8633:11:8633:26|*Output axi_s1_awready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8638:11:8638:25|*Output axi_s1_wready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8639:30:8639:41|*Output axi_s1_bid_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8640:17:8640:30|*Output axi_s1_bresp_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8641:11:8641:25|*Output axi_s1_bvalid_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8654:11:8654:26|*Output axi_s1_arready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8655:30:8655:41|*Output axi_s1_rid_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8656:32:8656:45|*Output axi_s1_rdata_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG781 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd.v":813:15:813:29|Input ahbl_hlock_i on instance spi_flash1_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd.v":555:30:555:80|*Input un1_axi_interconnect_0_inst_AXI_M03_interconnect_RDATA[255:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd.v":530:30:530:80|*Input un1_axi_interconnect_0_inst_AXI_M02_interconnect_RDATA[255:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd.v":505:30:505:80|*Input un1_axi_interconnect_0_inst_AXI_M01_interconnect_RDATA[255:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd.v":701:31:701:67|*Input un1_cpu_inst_AXI_M_DATA_interconnect_BID[3:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd.v":703:31:703:67|*Input un1_cpu_inst_AXI_M_DATA_interconnect_RID[3:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd.v":724:31:724:68|*Input un1_cpu_inst_AXI_M_INSTR_interconnect_BID[3:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd.v":726:31:726:68|*Input un1_cpu_inst_AXI_M_INSTR_interconnect_RID[3:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL246 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8581:17:8581:31|Input port bits 31 to 17 of axi_s0_awaddr_i[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8602:17:8602:31|Input port bits 31 to 17 of axi_s0_araddr_i[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8702:9:8702:24|*Input mem0_axi_error_i to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8758:9:8758:23|*Input arb_s1_awpipe_o to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8722:30:8722:45|*Input mem1_axi_waddr_o[14:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8721:9:8721:24|*Input mem1_axi_wr_en_o to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8724:30:8724:47|*Input mem1_axi_byte_en_o[3:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8723:30:8723:45|*Input mem1_axi_wdata_o[31:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8759:9:8759:23|*Input arb_s1_arpipe_o to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8725:9:8725:24|*Input mem1_axi_rd_en_o to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":8726:30:8726:45|*Input mem1_axi_raddr_o[14:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21121:12:21121:20|Pruning register bits 4 to 0 of EBR_CTRL[7].ebr_wr_count[7][15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21121:12:21121:20|Pruning register bits 4 to 0 of EBR_CTRL[6].ebr_wr_count[6][15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21121:12:21121:20|Pruning register bits 4 to 0 of EBR_CTRL[5].ebr_wr_count[5][15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21121:12:21121:20|Pruning register bits 4 to 0 of EBR_CTRL[4].ebr_wr_count[4][15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21121:12:21121:20|Pruning register bits 4 to 0 of EBR_CTRL[3].ebr_wr_count[3][15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21121:12:21121:20|Pruning register bits 4 to 0 of EBR_CTRL[2].ebr_wr_count[2][15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21121:12:21121:20|Pruning register bits 4 to 0 of EBR_CTRL[1].ebr_wr_count[1][15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21121:12:21121:20|Pruning register bits 4 to 0 of EBR_CTRL[0].ebr_wr_count[0][15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL177 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":21177:4:21177:9|Sharing sequential element dpram_wraddr and merging dpram_wrdata. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL260 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":838:16:838:21|Pruning register bit 4 of wr_encode_async.wr_grey_sync_r[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":838:16:838:21|Pruning register bit 2 of wr_encode_async.wr_grey_sync_r[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\new_lpddr4\2.1.0\rtl\new_lpddr4.sv":19525:4:19525:9|Pruning register bits 8 to 7 of addr_count[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL246 :"C:\LAB3\WS\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\gpio0\1.6.1\rtl\gpio0.v":542:17:542:28|Input port bits 31 to 8 of apb_pwdata_i[31:0] are unused. Assign logic for all port bits or change the input port size.

