@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: FX493 |Applying initial value "0" on instance inputArea_target.
@N: FX493 |Applying initial value "0000" on instance jtag_tap_fsm_state[3:0].
@N: FX493 |Applying initial value "1111111111111111111111111111111111111111111111111111111111111111" on instance clint_cmp[63:0].
@N: FX493 |Applying initial value "010" on instance genblk3\.ahbl_hsize_p_r[2:0].
@N: FX493 |Applying initial value "000000000000000" on instance genblk3\.rd_prev_r[14:0].
@N: FX493 |Applying initial value "0" on instance genblk3\.ahbl_hresp_r.
@N: FX493 |Applying initial value "1" on instance genblk3\.ahbl_hreadyout_ext_r.
@N: BN362 :"c:\lab3\ws\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":6910:32:6910:37|Removing sequential instance genblk3\.genblk1\.genblk1\.addr_a_p_r[14] (in view: work.system0_ipgen_lscc_smem_lram_Z149_layer0(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
@N: BN362 :"c:\lab3\ws\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\system0\2.2.0\rtl\system0.v":6910:32:6910:37|Removing sequential instance genblk3\.genblk1\.genblk1\.addr_a_p2_r[14] (in view: work.system0_ipgen_lscc_smem_lram_Z149_layer0(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
@N: MO225 :"c:\lab3\ws\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\ip\gpio0\1.6.1\rtl\gpio0.v":321:16:321:21|There are no possible illegal states for state machine genblk1\.bus_sm_cs[3:0] (in view: work.gpio0_ipgen_lscc_apb2lmmi_8s_6s_1s_1_2_4_8_4s(verilog)); safe FSM implementation is not required.
@N: FX493 |Applying initial value "1" on instance genblk3\.bridge_sm_r[0].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[1].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[2].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[3].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[4].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[5].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[6].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[7].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[8].
@N: FX493 |Applying initial value "1" on instance genblk3\.bridge_sm_r[0].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[1].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[2].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[3].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[4].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[5].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[6].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[7].
@N: FX493 |Applying initial value "0" on instance genblk3\.bridge_sm_r[8].
@N: MF578 |Incompatible asynchronous control logic preventing generated clock conversion.
@N: FX1184 |Applying syn_allowed_resources blockrams=208 on top level netlist cpnx_riscv_rx_rd 
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
