@W: MT453 :"c:/lab3/ws/cpnx_riscv_rx_rd/impl_1/cpnx_riscv_rx_rd_impl_1_cpe.ldc":5:0:5:0|clock period is too long for clock osc0_inst_lf_clk_out_o, changing period from 31250.0 to 15625.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 15625.0 ns to 7812.5 ns. 
@W: MT536 |Found constraint file with both legacy-style and FPGA timing constraints. 
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: MT530 :"c:\lab3\ws\cpnx_riscv_rx_rd\cpnx_riscv_rx_rd\lib\latticesemi.com\module\apb_interconnect0\1.2.1\rtl\apb_interconnect0.v":2683:4:2683:9|Found inferred clock pll0_ipgen_lscc_pll_Z137_layer0|clkop_o_inferred_clock which controls 17717 sequential elements including apb_interconnect0_inst.lscc_apb_interconnect_inst.apb_bus\.u_lscc_apb_bus.u_lscc_apb_multiplexor.apb_psel_def_r. This clock has no specified timing constraint which may adversely impact design performance. 
