Project Settings
Project Name proj_1 Device Name impl_1: Lattice LFCPNX : LFCPNX_100
Implementation Name impl_1 Top Module cpnx_riscv_rx_rd
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 274 192 0 - 04m:25s - 10/18/2024
10:36 AM
(premap)Complete 34 4 0 0m:25s 0m:25s 496MB 10/18/2024
10:37 AM
(fpga_mapper)Complete 126 5012 0 06m:10s 06m:16s 714MB 10/18/2024
10:43 AM
Multi-srs Generator Complete00m:10s10/18/2024
10:36 AM

Area Summary
Register bits 19939 I/O cells 67
Block RAMs (v_ram) 52 DSPs (dsp_used) 4
LUTs (total_luts) 23939

Timing Summary
Clock NameReq FreqEst FreqSlack
cpu_ipgen_vex_jtag_bridge_LIFCL_14s_0s_0b1_0b0_0b0_0x04000|bbICH_inferred_clock200.0 MHz312.6 MHz1.802
cpu_ipgen_vex_jtag_bridge_LIFCL_14s_0s_0b1_0b0_0b0_0x04000|bqAaKcoy7LeAHb1_inferred_clock200.0 MHz292.1 MHz0.788
new_lpddr4_ipgen_clock_sync_1s_4s_0s_4|sclk_o_inferred_clock200.0 MHz152.2 MHz-1.571
osc0_inst_hf_clk_out_o50.0 MHzNANA
osc0_inst_lf_clk_out_o0.1 MHzNANA
pll0_ipgen_lscc_pll_Z137_layer0|clkop_o_inferred_clock200.0 MHz41.4 MHz-19.169
spi_flash1_inst_spi_clk50.0 MHz54.4 MHz1.103
System200.0 MHz189.7 MHz-0.273

Optimizations Summary
Combined Clock Conversion 1 / 5